Recommended topology when 2 chips DDR3 are connected to i.MX6.

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Recommended topology when 2 chips DDR3 are connected to i.MX6.

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satoshishimoda
Senior Contributor I

Hi community,

Our partner have a question about i.MX6 series DDR3 connection.

They want to know the recommended topology when two chips DDR3 are connected to i.MX6.

In this case, should they use fly-by topology? or T-branch topology?

I feel fly-by topology is better because write leveling can use to it, but could you let me know Freescale recommendation?

Best Regards,

Satoshi Shimoda

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aven_tsao
NXP Employee
NXP Employee

Hi Satoshi:

Both T-topo and Fly-By design are ok in 2 ddr chips case.

But we suggest use T-topology design in 4 (and 2) ddr chips case, because the Fly-by design need additional power supply for external termination resistors.

(It will increase the cost and power consumption).

Please reference to the section 3.5 Routing considerations in MX6 HDG for the detail.

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf?fasp=1&WT_TYPE=Users Guides&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf

Best regards

Aven

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aven_tsao
NXP Employee
NXP Employee

Hi Satoshi:

Both T-topo and Fly-By design are ok in 2 ddr chips case.

But we suggest use T-topology design in 4 (and 2) ddr chips case, because the Fly-by design need additional power supply for external termination resistors.

(It will increase the cost and power consumption).

Please reference to the section 3.5 Routing considerations in MX6 HDG for the detail.

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf?fasp=1&WT_TYPE=Users Guides&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf

Best regards

Aven

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