RGMII to RGMII connection

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RGMII to RGMII connection

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niteshsahay
Contributor III

Hi

In my project i am planning to have MAC to MAC communication (i.e. RGMII) with MCIMX6QP6AVT1AA.

Any idea on how to connect the pins for MAC to MAC communication.

Regards

Nitesh

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Pavel
NXP Employee
NXP Employee

Look at the following document:

http://www.nxp.com/files/ftf_2010/Americas/WBNR_FTF10_NET_F0568.pdf

Find the "RGMII without a PHY" in this document.

The i.MX6 requires external signal ENET_REF_CLK.

The following connection is needed:

  1. i.MX6 <=> i.MX6

TXDx      => RXDx

RXDx      <= TXDx

TX_EN        => RX_DV

RX_DV        <= TX_EN

TX_ER => RX_ER

RX_ER <= TX_ER


Have a great day,
Pavel Chubakov

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RichG
Contributor III

Hello,

Is there a better link to the document that is referenced in this topic? The link appears to be broken. I'm looking at using an RGMII to RGMII connection between two i.MX8QM processors - I assume that will work similarly? Also, is there anything special that I need to do regarding the software? Since there is no MDC/MDIO connection I'm guessing there might be. 

Thanks so much,

Rich

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niteshsahay
Contributor III

Hi Pavel

Thanks for the reply.

I am attaching one file can you please help me out in cross verifying the connections i have made for my board (i.e. MAC to MAC).

Another one query regarding TXC and RXC clock i.e. 125MHZ clock will be externally given or how it is?

BR\NiteshRGMII Interface_MAC to MAC.png

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Pavel
NXP Employee
NXP Employee

Yes, External 125 MHz clock source is needed. Find the "RGMII without a PHY" in the following document:

http://www.nxp.com/files/ftf_2010/Americas/WBNR_FTF10_NET_F0568.pdf
Have a great day,
Pavel Chubakov

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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niteshsahay
Contributor III

Hi Pavel

Thanks for the reply.

One query on Clock:

1) Only single oscillator can be used to generate 125 MHz for TXC and RXC or two different oscillators are used to connect TXC and RXC.

2) Can we have one zero clock delay to generate two output which will be individually connected to TXC and RXC.

BR\Nitesh

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Yuri
NXP Employee
NXP Employee

Hello,

   it is enough to provide common for both i.MX6 parts ENET_REF_CLK.

Regards,

Yuri.

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