Question about enable 4 DMIC on i.MXRT1170EVK

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Question about enable 4 DMIC on i.MXRT1170EVK

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Shawn_
Contributor I

Hi all,

I'm now learning to use DMICs on RT1170-EVK. In "pdm_sai_multi_channel_edma_cm7" Demo, there are 2 DMICs enabled, and I want to enable 4 DMICs, I have done following changes, but it doesn't work, and there is also no error when I debug the code. Is there any Demo for 4 DMICs? Thanks and Regards!

DMIC_PIN.PNGPDM_DMIC.png

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jingpan
NXP TechSupport
NXP TechSupport

Hi @Shawn_ ,

It seems there isn't such a demo.

Since you want to use 4 PDM channels, you should enable the other two channels. Each channel is enabled by PDM_TransferSetChannelConfigEDMA() in this demo.

And you should let DMA transfer the two channels data too.  PDM has only one DMA trig signal. So, it use DMA scatter gather mode to collect data from each channel's FIFO. The new channel you added also need TCD.

 

Regards,

Jing

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Shawn_
Contributor I

Hi Jing,

Thanks for your answer, I still haven't been able to successfully drive four DMICs. I still have some questions about PDM and DMIC and hope to get your help. My understanding of PDM and DMIC on RT1170 is that RT1170 has four PDM channels, two MIC_CLK, each PDM channel can support up to two DMIC channels, one PDM can enable one DMIC alone, and one PDM can also enable 2 DMICs, each MIC_CLK can support two PDM channels (that is, up to four DMICs). One MIC_CLK and four DMIC_DATA are provided on RT1170-EVK, that is, if I want to use four DMICs, I can either create two PDM channels with two DMICs connected to each channel, or I can create four PDMs channels, each channel is connected to a DMIC. Four DMICs share MIC_CLK. Is my understanding correct?

PDM.pngDMIC_Interface.PNGDMIC_MCU.PNG

In the demo of RT1170EVK(pdm_sai_multi_channel_edma_cm7&pdm_sai_edma_cm7), only one or two DMICs (U40&U41) are used. Therefore, only "#define DEMO_PDM_EDMA_CHANNEL_0 0" is used in the code to create a PDM channel to enable one or two DMICs. Only GPIO_LPSR_09_MIC_BITSTREAM0 and GPIO_LPSR_08_MIC_CLK are initialized in pin_mux.c. According to the schematic diagram, the signals of the two DMICs U40 and U41 can be passed to the MCU either through DMIC_DATA0 or DMIC_DATA1. The current demo uses DMIC_DATA0. I tried to change DMIC_DATA0 (GPIO_LPSR_09) to DMIC_DATA1 (GPIO_LPSR_10) when configuring the pins, but I couldn't drive U40 and U41. So I would like to ask, in the current Demo, how to match DMIC_DATA0 (GPIO_LPSR_09) with DEMO_PDM_EDMA_CHANNEL_0? If I want the signals of U40 and U41 to be passed to the MCU through DMIC_DATA1, besides changing DMIC_DATA0 to DMIC_DATA1 in MCUXpresso Config Tool, and changing DEMO_PDM_EDMA_CHANNEL_0 to DEMO_PDM_EDMA_CHANNEL_1 in the code, what else do I need to modify to match DEMO_PDM_EDMA_CHANNEL_1 and GPIO_LPSR_10? 

Pin Settings in the DemoPin Settings in the Demomy Pin Settingmy Pin Setting1647359966050.png

1647360019791.png1647360096246.pngThanks and Regards

 

 

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jingpan
NXP TechSupport
NXP TechSupport

Hi @Shawn_ ,

It should say there are 8 PDM channels which can connect to 8 DMIC.

There are 4 data line. Each data line can connect to two DMIC. Left DMIC data is picked at rising edge of the MIC_CLK and right DMIC data is picked up at falling edge. Please see Figure 56-2.

There is only one PDM clock which is shared by all DMIC. Please refer to Figure 56-1.

So, if you check the schematic again, you'll find R265 is DNP. That means it is not there. If you want to try DMIC_DATA1, you should attach it on.

 

Regards,

Jing

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