Problem in Programming uboot on Custom Board based on MT29F8G16ADAD Nand Flash through ATK

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Problem in Programming uboot on Custom Board based on MT29F8G16ADAD Nand Flash through ATK

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chandansingh
Contributor II

Hi All,


We have designed custom boards based on iMX257 with MT29F8G16ADADH4,
MT29F4G08ABADAH4 and MT29F8G08ADBDAH4 NAND Flashes.

Details of MT29F8G16ADAD :
Page size = 2K(Main) + 64 bytes(Spare Area)
No of pages in a block = 64
total size = 1 GB
Bus width = 16

Value of Configuration registers and some other related fields are -->
scan_pg_num = 1,    
bbi_page_offset = 0,
bbm_offset         = 0,

(1) NFC_RAM_BUF_ADDR = 0
(2) NFC_ULOCK_START_BLK0 = 0
(3) NFC_ULOCK_END_BLK0 = 0xFFFF
(4) NFC_NF_WR_PROT = 4
(5) NFC_CONFIGURATION = 2
(6) NFC_NF_CONFIG1 = 0x0A1B
(7) NFC_REG_SPAS = 0x20
(8) CCM_RCSR |= NF_16BIT; /* Set to 16-bit NAND */

While programming Uboot through ATK, RESET and READ ID commands are executed successfully(I am able to recieve the five bytes correctly after sending READID command). Now to progam, initially 1st page of each block has to be read to find that whether the Block is Good or Bad.

During this operation(Reading of 1st page of each block),reading is successful for 1st page of 1st block but after this during reading of 1st page of 2nd block, there is no interrupt bit SET and processor just wait infinitely for Interrupt bit (D15) of CONFIG2 register to be SET.

However with the same setting of configuration registers, I was able to program Board with Nand flash MT29F8G08ADBDAH4.

Few more observations -->
While reading Page1 of Block2,iMX257 is able to read 512bytes(Confirmed by observing signal RE#, CE# and R/B#) after sending page read related commands (0x00h, Col Addr1,Col Addr2, Row Addr1,Row Addr2, Row Addr3 and 0x30h ). But not next remaining 512*3 = 1536 bytes. Neither RE# nor CE# goes LOW.


Thanks & regards,

Chandan Singh


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Yuri
NXP Employee
NXP Employee

Some comments regarding register settings :

NAND_FLASH_CONFIG1[PPB] = 01 - 64 pages per block.

Note, the i.MX25 NFC considered all NANDs as one of 512 bytes pages.

All operations are provided as sequence of 512-byte (+16 spare) accesses.

So, please try NAND_FLASH_CONFIG1[PPB] = 11 - 256 pages per block, in order to get correct block size for erasing. 

Also it is needed to issue 4 (x 512 bytes) accesses to get full 2K page.

SPAS should be set to 64 for a 2 Kbyte SLC device.

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Yuri
NXP Employee
NXP Employee

Some comments regarding register settings :

NAND_FLASH_CONFIG1[PPB] = 01 - 64 pages per block.

Note, the i.MX25 NFC considered all NANDs as one of 512 bytes pages.

All operations are provided as sequence of 512-byte (+16 spare) accesses.

So, please try NAND_FLASH_CONFIG1[PPB] = 11 - 256 pages per block, in order to get correct block size for erasing. 

Also it is needed to issue 4 (x 512 bytes) accesses to get full 2K page.

SPAS should be set to 64 for a 2 Kbyte SLC device.

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