Power Up Questions and Confirmations for i.MX6

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Power Up Questions and Confirmations for i.MX6

Contributor III

1. We were initially concerned about allowing a USB OTG device to present 5V on VBUS to the iMX6 while the system is powered down. So we added a load switch to gate the power to the iMX6 with the enable wired to the GEN_3V3 output of the PMIC. This ensures that the iMX6 has all of its core rails (i.e. VDDSNVS, VDDCORE, VDDSOC, VDDR, and GEN_3V3) before 5V is ever applied to the OTG VBUS pins of the iMX6. Is this both necessary and sufficient?

2. We supply USB Host 5V VBUS to the iMX6 via a dedicated regulator on our system board. Similar to #1 above, at what point in the PMIC power on sequence is it safe to turn on this power rail to the iMX6? We presently plan on waiting until the sequence is completely finished.

3. Since the SOM PMIC supplies GEN_VSNVS from VSYS input once it is present and greater than the LICELL input, can we remove the LICELL power source after VSYS has been applied to save power on our end. Note we supply LICELL from an LDO. We do not have a battery and do not need PMIC RTC functionality.

4. Once VSYS is applied, the PMIC will automatically begin sequencing on all of the power supplies. It has been suggested by Al that if the PMIC PWRON input is held low at this point, the PMIC will still sequence up the supplies but gate the outputs (somehow) until the signal is released, then enable them all in parallel with the release of PWRON. This behavior doesn’t make sense to me as it defeats the purpose of sequencing in the first place. It makes more sense that the PMIC would hold off the start of the sequence until the PWRON signal is released. What is the actual behavior in this scenario?

5. Section 50.5 of the iMX6 TRM states the following:

If VDDHIGH_IN is present, then the SNVS_IN supply is internally shorted to the VDDHIGH_IN supply to allow coin cell recharging if necessary.

Is this only done in the charging case? In the SOM design, this will bypass the D1 diode drop from GEN_3V3 to GEN_VSNVS, shorting those two separate supply outputs from the PMIC. The GEN_VSNVS rail value is 3.0V nominal while the GEN_3V3 is 3.3V. Therefore, the (iMX6 internal) shorting of these two supplies seems problematic. Can you please clarify what is going on here? It’s not clear how this would work even in the LICELL charging case since the charger in the PMIC runs off the VIN that supplies the GEN_VSNVS LDO. Maybe this does not apply to our configuration?

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NXP Employee
NXP Employee

Hi Adam

1.2. In i.MX6 (opposite to other i.MX) USB VBUS can be powered any time,

even to unpowered processor. From IMX6DQCEC sect.4.2.1 Power-Up Sequence

USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply

sequence and can be powered at any time.

3. You can remove LICELL power, however 0.1uF capacitor should be connected to it :

sect. MMPF0100 . This capacitor provides power to PMIC core during

glitches on VIN.

AN4717 AN4717, Schematic Guidelines for the MMPF0100 - Application Note

4. I never saw such descriptions in Docs. You are correct that

"PMIC would hold off the start of the sequence until the PWRON signal is released."

This is correct PMIC behaviour.

5. Internal shorting of SNVS_IN to VDDHIGH_IN Explanation Needed

Best regards


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