Performance of using Fly-By topology for DDR3 with iMX7D

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Performance of using Fly-By topology for DDR3 with iMX7D

Contributor I


I saw in the Hardware Development Guide that Fly-By topologies are not recommened for designs using iMX7D processors. However, my design is very limited on how and where I can place components or route signals. What will happen if the only way to route the DDR3L is by using Fly-By techniques? Will the design not work at all, or will the speed be limited?

Thanks, Amos

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NXP TechSupport
NXP TechSupport

Hello Amos,

The fly-by topology for DDR3 is not supported on the i.MX7D as the memory controller is not capable of automatically calibrating each DQS strobe to arrive at the DRAM in phase with the SDCLK signal. This calibration is critical for the DDR3 to work at any speed. The most likely scenario would be that the DDR3 wouldn’t work correctly so I would recommend looking for alternatives that may allow the t-topology.

I understand that there are constraints on your design but DDR is probably the hardest interface to route precisely due to how its timing is critical.

My apologies for the inconvenience.


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