PINMUX generation using NXP tool

[vivekvix]

We are building a custom board using the Imx8mp processor. 

I was going through the device tree thats present in the source and came across the pin mux configuration in the dts and the dtsi files.

Example snippet from dts: 

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_hog>;

pinctrl_ecspi2: ecspi2grp {

fsl,pins = <

MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82

MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82

MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82

>;

};

pinctrl_ecspi2_cs: ecspi2cs {

fsl,pins = <

MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000

>;

};

pinctrl_gpio_led: gpioledgrp {

fsl,pins = <

MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19

MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19

MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x19

MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x19

MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x19

>;

};

After going through the datasheets and reference manuals and some digging on the internet i came across the NXP provided pin config tool which generates the PIN mux config also. 
But when I select these pins (for ex ECSPI2) the Pinmux tool generates completely different addresses.
And weirdly its generating the same address (106) nomatter what peripheral I add. (Snippet below)

So in actuality how do I get these addresses of these pins?
How do i proceed further to add our own peripherals to the custom board??
How can i add these adresses as a part of the device tree and get the board working?

[AldoG]

Hello,

If you want to know the address you may refer to this file:
https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h

This macros definitions have the address for the Muxing of the pads.

You may use this file and the reference manual for correct Muxing and pad configuration for your custom board.

Saludos,
Aldo.

[vivekvix]

Even After going through the file I've not exactly understood how to get the adresses, as I'm looking at one of the dts files which uses the imx8mp (i.e the humming board pulse from solidrun), say ecspi2 node

&iomuxc {

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_hog>;

pinctrl_ecspi2: ecspi2grp {

fsl,pins = <

MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82

MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82

MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82

>;

};

pinctrl_ecspi2_cs: ecspi2cs {

fsl,pins = <

MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000

>;

};

How did These adresses arrive? 0x82 and 0x40000
Why do all the SCLK, MOSI, MISO have same adresses
Why do the adresses of the above 3 and CS look different?

Also, say i want to reconfigure one of the SAI pins as a GPIO and add the node in my dts, how can i get the adresses? How can i do it? Or more simply put how can i take any pin from the processor configure it as either an LED or a pushbutton?

Please provide us an elaborate answer as we are facing trouble regarding the same and we don't have much support...Thanks in advance!  

[AldoG]

Hello,

Please note that you're confusing the macro wich have the register address for the actual mux, and the configuration of such pin.

Each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val input_val> are specified using a PIN_FUNC_ID macro, which can be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>.

The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.

Example:
pinctrl_uart2: uart2grp {
fsl,pins =
<0x228 0x488 0x5F0 0x0 0x6 0x49>,
<0x228 0x488 0x000 0x0 0x0 0x49>;
};

Hope this helps,
Best regards/Saludos,
Aldo.

[vivekvix]

Thank you so much for the elaborate reply.
That answered most of my questions. 

But after going through the reference manual also, i was unable to find any information related the last integer CONFIG pad setting value. 

Is there any standard values for set peripherals or it is listed in some document?

[AldoG]

Hello,

Glad to hear that it helped, for the CONFIG value you may refer to the reference manual, chapter 8.2.4 IOMUXC Memory Map/Register Definition.

In this chapter you'll find three types of register 
SW MUX Control
SW PAD Control
Daisy

For the CONFIG you may check the SW PAD Control for each pad, note that it is almost the same for all pads, but please double check the values you want to have are correct.

Best regards/Saludos,
Aldo.