Attached are files that will help with setting up i.MX28 and i.MX50 memory controller for different memory types.
Original Attachment has been moved to: MX28_mDDR_register_programming_aid_v0.4.zip
Original Attachment has been moved to: MX50_DRAM_controller_register_programming_aid.zip
I came across this discussion while searching for MX28 DDR2 register programming file.
We have 4 Micron MT47H256M8EB-25EIT on our board, total 1GByte, and running at about 130MHz.
Currently we have some issues with our board. We suspect it's the DDR2 memory issue and could be related to register setting.
I have setup the attached register programming file. Can anyone please help and check to see if I have the registers setup correctly?
I think, it makes sense to create separate request (to check memory configuration; also, please attach
(CPU <-> DRAM) schematic).
Is it correct in DQS_N_EN=1?
I think mDDR to be Single-ended DQS.
Is there a similar ddr initialization aid for i.MX28 interfacing to DDR2?
I'm particularly interested in setting of HW_DRAM_CTL176 and how those should be set relative to Taond, Taofd, Taofpd, Taonpd, Tanpd, etc from the ddr2 datasheet.
Is there a similar guide for imx25?
I'm working on supporting 256MB RAM (mddr) for this chipset and not sure if it's supports it.
section 24.1.9 of imx25 reference manual says Up to "128 Mbytes per chip select"
Thx for the quick response.
In particular I wanted to know if 256M of RAM is supported on a single chip select by mx25(I'm using a 4bank 16*16M ) H5MS1G62MFP-E3M
I am afraid this is impossible to have 256 Mbytes with i.MX25, using single chip select.
There are the next restrictions of i.MX25 memory controller :
1) i.MX25 only can support 4-banks ;
2) i.MX25 has a 16-bit data bus ;
3) maximum Row address width is 14 bit ;
4) maximum Column address width is 10 bit.
This means maximum 128 Mbytes per CS.