MMPF0100 output voltages power off order.

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MMPF0100 output voltages power off order.

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satoshishimoda
Senior Contributor I

Hi community,

I have a question about MMPF0100.

I knew MMPF0100 output voltage will be power off from smaller voltage to largest voltage in order in Is i.MX6SL damaged if power-down sequence is not observed without MMPF0100.

However, I thought all  MMPF0100 output are powered off simultaneously if power supply for MMPF0100 is stopped.

So I did not understand how the power off order is generated.

Would you kindly let me know how the power off order is generated?

Best Regards,

Satoshi Shimoda

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art
NXP Employee
NXP Employee

Actually, the power-down sequences, shown in the Section 4.2.2 "Power-Down Sequence" of the i.MX6SoloLite Data Sheet Rev.3 document, are just the example ones. For correct chip shutdown, all supply voltages can just start to ramp down simultaneously. And, in case of momentarily removing the main power from the PF0100 PMIC, the supplies with lower output voltages and higher load, e.g. VDD_ARM_IN, VDD_SOC_IN and VDD_PU_IN core supply voltages, will ramp down faster than the supplies with the higher output voltages (e.g. I/O supply voltages). So, generally, there is no any contradiction here.


Have a great day,
Artur

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reyes
NXP TechSupport
NXP TechSupport

Hi Satoshi,

There is no power-off sequence/order on the MMPF0100 because it depends on charge level on the output capacitors and inductors. Energy still accumulated inside the capacitors and inductors that start to discharge at the moment you turn off the MMPF0100.


Have a great day,
Jose Reyes

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satoshishimoda
Senior Contributor I

Hi Jose Reyes,

Thank you for your reply.

I understood MMPF0100 supports i.MX6SL power-down sequence by communication in MMPF0100 can satisfy i.MX6SL power-down sequence? , and Is i.MX6SL damaged if power-down sequence is not observed without MMPF0100.

But according to your reply, MMPF0100 cannot support i.MX6SL power-down sequence if lose the power supply for MMPF0100.

Would you re-check which is correct?

Best Regards,

Satoshi Shimoda

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art
NXP Employee
NXP Employee

Actually, the power-down sequences, shown in the Section 4.2.2 "Power-Down Sequence" of the i.MX6SoloLite Data Sheet Rev.3 document, are just the example ones. For correct chip shutdown, all supply voltages can just start to ramp down simultaneously. And, in case of momentarily removing the main power from the PF0100 PMIC, the supplies with lower output voltages and higher load, e.g. VDD_ARM_IN, VDD_SOC_IN and VDD_PU_IN core supply voltages, will ramp down faster than the supplies with the higher output voltages (e.g. I/O supply voltages). So, generally, there is no any contradiction here.


Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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satoshishimoda
Senior Contributor I

Dear Artur,

Thank you for your reply.

According to your reply, i.MX6SL have same power-down sequence as other i.MX6 series (i.MX6SDL, i.MX6DQ), right?

Best Regards,

Satoshi Shimoda

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