KSZ8863 Phy 1 not found on u-boot

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KSZ8863 Phy 1 not found on u-boot

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wenmingfeng
Contributor III

Hi ,

I am using imx_3.14.52_1.1.0_ga uboot for bring up our imx6dl customer board, the eth phy is ksz8863. 

It shows the phy 1 not find but command mii can detect it. What is wrong with my setup? 

the pad I am used is as below, and the console print out also paste.

MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* KSZ8863 PHY Reset */
MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),

U-Boot 2015.04 (Jan 26 2017 - 12:54:30)

CPU: Freescale i.MX6DL rev1.3 at 792 MHz
CPU: Temperature 36 C
Reset cause: POR
Board: MX6-SabreSD
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
wf@ ret:1
auto-detected panel HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
wf@ ret:1
switch to partitions #0, OK
mmc0 is current device
Net: wf@interface:7 phy_mask:0x2
Phy 1 not found
FEC
Normal Boot
Hit any key to stop autoboot: 0
=> mii
mii - MII utility commands

Usage:
mii device - list available devices
mii device <devname> - set current device
mii info <addr> - display MII PHY info
mii read <addr> <reg> - read MII PHY <addr> register <reg>
mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>
mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)
Addr and/or reg may be ranges, e.g. 2-7.
=> mii info
PHY 0x01: OUI = 0x0885, Model = 0x03, Rev = 0x00, 100baseT, FDX
PHY 0x02: OUI = 0x0885, Model = 0x03, Rev = 0x00, 10baseT, HDX
PHY 0x03: OUI = 0x0885, Model = 0x03, Rev = 0x00, 100baseT, FDX
=>

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi wenming

please try to set in uboot/include/configs/board.h :

#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL

as for example in mx6ullevk.h

uboot-imx.git - Freescale i.MX u-boot Tree 

Best regards
igor
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wenmingfeng
Contributor III

Hi Igor,

Thanks for your quick response. I add the defines but the same result. 

The Reference clk we used is from phy and input at FEC_TX_CLK pin.

Shall I program settings about the ANATOP ?

Thanks!

Wenming

pastedImage_1.png

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Wenming

please check uboot patches with descriptions in MX6_enet_RMII.zip on
https://community.nxp.com/thread/304346?commentID=331971#comment-331971 

Best regards
igor

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wenmingfeng
Contributor III

Hi Igor,

Thanks for your information. The uboot version I am used is 3.14.52_1.1.0_ga. The kernel driver seems find the phy and show fec100 ready with irq=-1. But can not send out packets, it stock at requesting dhcp. Can you point me out is this a software issue or I need to check the HW side?

Best regards!

Wenming

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Wenming

is it working in uboot, one check signals with oscilloscope

Best regards
igor

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wenmingfeng
Contributor III

Hi Ignor,

I checked the registers I used in the EnetPad, the value is as the IMX6SDLRM.pdf, I checked the net driver, for RMII mode working, I see below piece of code in fec_mxc.c function fec_open.

questions is shall I use this code or not? I am not sure whether I need it or not.

#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) 
udelay(100);
/*
* setup the MII gasket for RMII mode
*/

/* disable the gasket */
writew(0, &fec->eth->miigsk_enr);

/* wait for the gasket to be disabled */
while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
udelay(2);

/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);

/* re-enable the gasket */
writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);

/* wait until MII gasket is ready */
int max_loops = 10;
while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
if (--max_loops <= 0) {
printf("WAIT for MII Gasket ready timed out\n");
break;
}
}
#endif

Thanks!

Wenming

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wenmingfeng
Contributor III

The uboot code of 3.14.52 need to modified for phys to make it working. donot use CONFIG_PHYLIB  and use fixed speed.

in my case is in fec_open(){\

#ifdef CONFIG_PHYLIB
{
/* Start up the PHY */
int ret = phy_startup(fec->phydev);

if (ret) {
printf("Could not initialize PHY %s\n",
fec->phydev->dev->name);
return ret;
}
speed = fec->phydev->speed;
}
#else
#if 1 //as microchip
miiphy_wait_aneg(edev);
speed = miiphy_speed(edev->name, fec->phy_id);
miiphy_duplex(edev->name, fec->phy_id);
#else
speed=100;
#endif
#endif

#ifdef FEC_QUIRK_ENET_MAC
{
#if 0
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
if (speed == _1000BASET){
ecr |= FEC_ECNTRL_SPEED;
// printf("wf@fec_open speed==1000BASET\n");
}
else if (speed != _100BASET){
rcr |= FEC_RCNTRL_RMII_10T;
// printf("wf@fec_open speed!=100BASET\n");
}
// printf("wf@fec_open ecr:%x rcr:%x\n",ecr,rcr);
writel(ecr, &fec->eth->ecntrl);
writel(rcr, &fec->eth->r_cntrl);
#endif
}
#endif
debug("%s:Speed=%i\n", __func__, speed);

/*
* Enable SmartDMA receive task
*/
fec_rx_task_enable(fec);

udelay(100000);
return 0;
}

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wenmingfeng
Contributor III

Hi Igor,

It is still not working in uboot, even in kernel not working. I check the signals on the ksz8863 pins, it is the same with our imx53 customer board, the only difference is that imx6dl we used the GPIO_1_IO08 as the INT pin.  Is someone else also used the RMII enet has same issue?

Thanks!

Wenming

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