Is it feasible to use SAI2 input MCLK as the root clock of PDM on i.MX 8M Plus?

[ZenJeams]

hi NXP,

Is it feasible to use SAI2 input MCLK as the root clock of PDM on i.MX 8M Plus? and if so, how to configure it？

Thank you.

[Alejandro_Salas]

Hello @ZenJeams 

You can check the 14.1.1.1 SAI Master Clock Inputs/Outputs from Reference Manual:

The MCLK pin on each SAI module can be configured as either an input or an output.
When configured as an output, the SAIn_CLK_ROOT from the CCM or the
MCLK_OUT from SAIn is routed to the pad output. Note that the SAIn_MCLK_OUT is
always derived from the ipg_clk_sai_mclk (MCLK[1]) input. When configured as an
input, the external input to the pad will be used as SAIn_MCLK and is routed to
SAIn_MCLK_IN, which can be used as master clock for SAI. Below is a diagram
showing both input and output options.

Best reagrds.

Salas.

[ZenJeams]

I made the following changes in my DTS configuration file according to the Reference Manual,

1.Set SAI2 MCLK input.

2.Link SAI2 MCLK with SAI1  MCLK2.

3.Set SAI1 MCLK as PDM root clock.

but the following error occurred when I was recording with imx-audio-micfil audio card.

[   21.797982] fsl-micfil-dai 30ca0000.micfil: reached a null clock

[   21.797993] fsl-micfil-dai 30ca0000.micfil: failed to set mclk[12000000] to rate 1024000

[   21.798000] fsl-micfil-dai 30ca0000.micfil: ASoC: error at snd_soc_dai_set_sysclk on 30ca0000.micfil: -22

[   21.798005] imx-card sound-micfil: failed to set cpui dai mclk1 rate (1024000): -22

[   21.798009]  micfil hifi: ASoC: error at snd_soc_link_hw_params on micfil hifi: -22

[   21.798025]  micfil hifi: ASoC: soc_pcm_hw_params() failed (-22)

[   70.352711] fsl-micfil-dai 30ca0000.micfil: reached a null clock

[   70.352722] fsl-micfil-dai 30ca0000.micfil: failed to set mclk[12000000] to rate 1024000

[   70.352728] fsl-micfil-dai 30ca0000.micfil: ASoC: error at snd_soc_dai_set_sysclk on 30ca0000.micfil: -22

[   70.352734] imx-card sound-micfil: failed to set cpui dai mclk1 rate (1024000): -22

[   70.352737]  micfil hifi: ASoC: error at snd_soc_link_hw_params on micfil hifi: -22

[   70.352753]  micfil hifi: ASoC: soc_pcm_hw_params() failed (-22)

This is my configuration:

pinctrl_sai2: sai2grp {

fsl,pins = <

MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6

MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6

MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6

MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6

MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x40000106

>;

};

&sai1 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
assigned-clock-parents = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2_SEL 8>;
assigned-clock-rates = <12288000>;
fsl,txmasterflag = <1>;
fsl,rxmasterflag = <1>;
status = "okay";
};

sai1: sai@30c10000 {
compatible = "fsl,imx8mp-sai", "fsl,imx8mm-sai";
reg = <0x30c10000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2_SEL>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
dma-names = "rx", "tx";
fsl,shared-interrupt;
fsl,dataline = <0 0xff 0xff>;
power-domains = <&audiomix_pd>;
status = "disabled";
};

micfil: micfil@30ca0000 {
compatible = "fsl,imx8mp-micfil";
reg = <0x30ca0000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>,
<&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_SEL 2>; // <&clk IMX8MP_CLK_EXT3>;
clock-names = "ipg_clk", "ipg_clk_app",
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
power-domains = <&audiomix_pd>;
status = "disabled";
};

&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MP_CLK_PDM>;
assigned-clock-parents = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_SEL 2>;
assigned-clock-rates = <12288000>;
status = "okay";
}

What's wrong with my configuration?

Thank you. 

[zouhui]

Hi NXP fellows,

Need you guys give strong support.

Following the IMX8MPRM document, SAI2 MCLK is configured as input, SAI1 MCLK use MCLK2 and select SAI2.MCLK, PDM clock root select SAI1_MCLK. 

To achieve the idea above, how to modify software for dts and other necessary files?