Internal shorting of SNVS_IN to VDDHIGH_IN Explanation Needed

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Internal shorting of SNVS_IN to VDDHIGH_IN Explanation Needed

Contributor III

Section 50.5 of the iMX6 TRM states the following:

If VDDHIGH_IN is present, then the SNVS_IN supply is internally shorted to the VDDHIGH_IN supply to allow coin cell recharging if necessary.

Is this only done in the charging case? In our SOM design, this will bypass the D1 diode drop from GEN_3V3 to GEN_VSNVS, shorting those two separate supply outputs from the PMIC. The GEN_VSNVS rail value is 3.0V nominal while the GEN_3V3 is 3.3V. Therefore, the (iMX6 internal) shorting of these two supplies seems problematic. Can you please clarify what is going on here? It’s not clear how this would work even in the LICELL charging case since the charger in the PMIC runs off the VIN that supplies the GEN_VSNVS LDO. Maybe this does not apply to our configuration?

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NXP Employee
NXP Employee

Hi Adam

some details can be found in IMX6DQ6SDLHDG Table 2-6

Regarding powering SNVS_IN with external LDO I do not see problems

here since LDO output transistor will be turned off, when it will see voltage

at SNVS_IN (LDO output) higher than expected. Typical PMIC VSNVS=3.0V

and SW2 (connected to VDDHIGH_IN is 3.15-3.3V)

In general one can consider just to add schottky diode in series with LDO output.

Regarding charger in the PMIC, it charges LICELL and it is different from

i.MX6 charging capability over SNVS_IN.

Best regards


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