IMXRT1064 Pin Muxing Options

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IMXRT1064 Pin Muxing Options

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745件の閲覧回数
Lukas_Frank
Senior Contributor I

Hi Dear Authorized,


I have a bunch of question related to Pin Muxing process for IMXRT1064 based on ENET.


Q1: What are the equivalents of GPIO1_IO09 and GPIO1_IO10 for ENET2? What should I use for ENET2 while configuring it instead GPIO1_IO09 and GPIO1_IO10?

Q2: How can I learn pin config value for ENET2 SetPinConfig? For example 0xB0E9U is used as default for ENET1. What is configValue for ENET2? Is there any definition table or sheet for such a process?

Q3: What happens if I don't set SetPingConfig as theoretically?

Q4: Is there an importance generally of enabling SetPinMuxing or SetPinConfig in spesified order? For example should I fit the patterns like these: Enable UART Configurations, Enable ENET, Enable SPI. Am I able to set in arbitrary order any pinmuxing options?

Q5: I set the pins as below for ENET2. Can I use both ENET separately with these configuration in EVK by switching them in code side? Is only "ENET" strictly exist on EVK? Are we able to use ENET2 with EVK ethernet port?

Thanks and Regards.

 

Codes are such below:

 

void BOARD_InitPins(void) {
  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03u */

  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B, 0U);

  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B, 0U);

  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_LPUART8_TX, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_LPUART8_RX, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B, 0U);

  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0x10B0U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0x10B0U);

  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0x10B0U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0x10B0U);

  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_10_LPUART8_TX, 0x10B0U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_11_LPUART8_RX, 0x10B0U);

  // Initializations for ENET - as seen in default example
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U); 
  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
    (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) 
      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) 
    );
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0xB0A9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0xB0A9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0x31U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB829U); 

  // Initializations for ENET2
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_ENET2_RDATA00, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_ENET2_RDATA01, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_ENET2_RX_EN, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_ENET2_TDATA00, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_ENET2_TDATA01, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_ENET2_TX_EN, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_ENET2_REF_CLK2, 1U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_ENET2_RX_ER, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_ENET2_MDC, 0U);
  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_ENET2_MDIO, 0U);

  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_ENET2_RDATA00, 0xB0E9U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_ENET2_RDATA01, 0xB0E9U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_ENET2_RX_EN, 0xB0E9U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_ENET2_TDATA00, 0xB0E9U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_ENET2_TDATA01, 0xB0E9U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_ENET2_TX_EN, 0xB0E9U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_ENET2_REF_CLK2, 0x31U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_ENET2_RX_ER, 0xB0E9U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_38_ENET2_MDC, 0xB0E9U);
  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_39_ENET2_MDIO, 0xB829U);
}

 

 

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721件の閲覧回数
jeremyzhou
NXP Employee
NXP Employee

Hi @Lukas_Frank ,
Thanks for your reply.
Q4) Am I able to set in arbitrary order any pinmuxing options?
-- Yes, you can.
Q5) Is only "ENET" strictly exist on EVK? Are we able to use ENET2 with EVK ethernet port?
-- The MIMXRT1064 EVK only contains one ENET port, so you can't use the ENET2.
Have a great day,
TIC

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3 返答(返信)
739件の閲覧回数
jeremyzhou
NXP Employee
NXP Employee

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1)When it comes to figuring out the configuration of pins, it's all in the RM, and you can use the MCUXpresso Config Tools tool to generate the code automatically.
2) Can I use both ENET separately with these configuration in EVK by switching them in code side?
-- Yes.
3) Is only "ENET" strictly exist on EVK? Are we able to use ENET2 with EVK ethernet port?
-- The MIMXRT1064 EVK only contains one ENET port, so you can't use the ENET2.
Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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725件の閲覧回数
Lukas_Frank
Senior Contributor I

Hi Dear @jeremyzhou ,

Could you please inform me for Q4 and Q5 ?

Thanks.

0 件の賞賛
722件の閲覧回数
jeremyzhou
NXP Employee
NXP Employee

Hi @Lukas_Frank ,
Thanks for your reply.
Q4) Am I able to set in arbitrary order any pinmuxing options?
-- Yes, you can.
Q5) Is only "ENET" strictly exist on EVK? Are we able to use ENET2 with EVK ethernet port?
-- The MIMXRT1064 EVK only contains one ENET port, so you can't use the ENET2.
Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------