Hi Dear Authorized,
I am curious about an issue for SetPinMux Configuration Essentials.
Is it possible to use "GPIO_AD_B0_08" for RTS of UART1? I know reference manual says that IOMUXC_GPIO_AD_B0_09 pin is required to set pin and it is possible by using "IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B" definition in "fsl_iomuxc.h". In this case I am able to use RTS functionality like below:
//Pin Mux Settings
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B, 0U);
...
//Set RTS
LPUART1->MODIR |= LPUART_MODIR_TXRTSE_MASK;
LPUART1->MODIR |= LPUART_MODIR_TXRTSPOL_MASK;
However, I just want to create a manual RTS like below if possible:
//New IOMUX Definition for Possible Usage
#define IOMUXC_GPIO_AD_B0_08_Something_Possible_RTS_UART1 0x00000000 (What Should I Set for Usage?)
...
//Pin Mux Settings
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_Something_Possible, 0U);
...
//Set RTS
LPUART1->MODIR |= LPUART_MODIR_TXRTSE_MASK;
LPUART1->MODIR |= LPUART_MODIR_TXRTSPOL_MASK;
I think that there is a correlation between LPUART->MODIR Register and available RTS definitions in fsl_iomuxc.h. Therefore, I want to know if above case possible.(using another pin as general purposes, in this case RTS usage). If it is possible could you please inform me about "How to SetPinMux GPIO_AD_B0_08 for UART1 RTS?"
Available Definitions in fsl_iomuxc.h
#define IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK 0x401F80DCU, 0x0U, 0x401F831CU, 0x1U, 0x401F8250U
#define IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x401F80DCU, 0x1U, 0x401F838CU, 0x1U, 0x401F8250U
#define IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x401F80DCU, 0x2U, 0, 0, 0x401F8250U
#define IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x401F80DCU, 0x3U, 0, 0, 0x401F8250U
#define IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1 0x401F80DCU, 0x4U, 0x401F8304U, 0x1U, 0x401F8250U
#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F8250U
#define IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x401F80DCU, 0x6U, 0, 0, 0x401F8250U
Thanks and Regards.
