IMX8MQ 4.14.98 MIPI-DSI clock limit

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IMX8MQ 4.14.98 MIPI-DSI clock limit

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Contributor IV


       I download  the 4.14.98 version of kernel  and find the commit about nwl-dsi.c file 

a5eec7c52105fe73274074d27d7b07dda2c748cf MLK-17537-6: drm/bridge: nwl-dsi: force valid clocks
a878d0ecb404b98e260fdff10b2d7a2b2cfeeacf MLK-17537-5: drm/bridge: nwl-dsi: correct crtc_clock when panel used
5b1d3e2abacb8d5434931cb8399401d40d480522 MLK-17537-4: drm/bridge: nwl-dsi: implement mode_valid()
2e7d7549cbedb69b94b8aee845934858aed7746b MLK-17537-3: drm/bridge: nwl-dsi: Remove some vars
e2ceceb503b56e2105e33934d869b68ece777261 MLK-20697: drm/bridge: nwl-dsi: Fix EOTP handling
da62aec92a8e06e238eacdb3b36a961a29c13916 MLK-19010: drm/bridge: nwl-dsi: Fix DSI long read
a2619a1333a0cc948ea589fce690f49eaa5f234f MLK-18850: drm/bridge: nwl-dsi: Fix bridge handling
ffff698815b8b4aa7d2e03557e81cb3175978b6c MLK-18543-1: drm/bridge: nwl-dsi: Add pm_runtime support
d13b9be310ae5ca432801879e512b9d9eef30b71 MLK-18357-2: drm/bridge: nwl-dsi: Add no_clk_reset property
4ef91335c342e6d18528863cafd4ccb3e4adf503 MLK-17589: gpu/imx: Fix DCSS+DSI suspend/resume
05ad7bb97e08186ce69ad1bae9204e052d56e82a MLK-18177-2: drm/bridge: nwl-dsi: Change init sequence for panel
45f8c8d7741e5e067a5e40fbc6995cf27abcc141 MLK-18106: drm/bridge: Fix nwl-dsi bridge handling

--- a/drivers/gpu/drm/bridge/nwl-dsi.c
+++ b/drivers/gpu/drm/bridge/nwl-dsi.c
@@ -151,6 +151,22 @@

static const char IRQ_NAME[] = "nwl-dsi";

+ * TODO: Currently, filter-out unsupported modes by their clocks.
+ * Need to find a better way to do this.
+ * These are the pixel clocks that the controller can handle successfully.
+ */
+static int valid_clocks[] = {
+ 162000,
+ 148500,
+ 135000,
+ 132000,
+ 108000,
+ 74250,
+ 49500,
+ 31500,

mxsfb_drv.c file set othear limit about clock too.

mxsfb_drv.c mxsfb_pipe_mode_valid
  * TODO: Currently, only modes with pixel clock higher or equal to
  * 74250kHz are working. Limit to these modes until we figure out how
  * to handle the rest of the display modes.
 if (clock < MIN_PIX_CLK)            /*#define MIN_PIX_CLK  74250000*/
  return MODE_NOCLOCK;

it means the mipi-clock  must  be 74250,108000 ,132000,135000,148500,162000.   

But now i want to convert MIPI-DSI to LVDS signal , the clock limit make it hard for me . 

Any suggest?

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817 次查看
Contributor II

Hi, does anyone have success with this patch?  I have applied it to 4.14.98 kernel, but still having issues such as below, which appear to be due to clock settings?


[ 2.508261] imx-drm display-subsystem: bound imx-dcss-crtc.0 (ops dcss_crtc_ops)
[ 2.515814] nwl_dsi-imx mipi_dsi@30A00000: Using DCSS as input source
[ 2.522285] nwl_dsi-imx mipi_dsi@30A00000: No bridge found, skipping encoder creation
[ 2.530199] imx-drm display-subsystem: bound mipi_dsi@30A00000 (ops imx_nwl_dsi_component_ops)
[ 2.538849] [drm] Cannot find any crtc or sizes
[ 2.543809] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 0


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NXP Employee
NXP Employee

Hi coin

one can try attached patches or try with latest L4.19.35 Documentation

nwl-dsi.c\bridge\drm\gpu\drivers - linux-imx - i.MX Linux kernel 

Best regards
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