On the mx6ull evk, there is a smaller QSPI-A NOR flash footprint (ref des# U303) that resides inside of the 8-bit NAND flash footprint (ref des#U302). So, on the mx6ull evk... folks choose to either leverage the QSPI-A NOR flash (default), or they remove the QSPI NOR flash at U303 and install 8-bit NAND flash at U302 - correct?
So... the big question is as follows...
Is it possible to design a IMX6ULL based board that has both QSPI-A NOR flash and 8-bit parallel NAND flash? ...and... design the board such that both interfaces are available to be leveraged at same time?
1. The QSPI-A NOR flash could hold U-boot, kernel/device tree,
2. The NAND flash could hold the file sytem.
My concern is... did the original mx6ull evk intentionally only allow either QSPI flash or NAND flash by design because there were pinmux limitations blocking use of both interfaces at the same time?
In looking at page 13 (last page) of the mx6ull evk's carrier module's schematic -> the ALT tables defining the pinmux options only offer 'rawnand.' and 'qspi_' signal groups on one common set of pins.
And... when we examine these signals in NXP 'Pin Tools' -> we are only offered to route these signals to the same one set of pins.
So... may I assume the answer to my above question is... 'No.' ...and... 'Folks must either choose QSPI ...or... parallel NAND flash memory interface.' ?
Thanks in advance,