IMX6ULL ECSPI Timings

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IMX6ULL ECSPI Timings

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jonhallam
Contributor I

I'm trying to understand what the maximum rate is that the IMX6ULL can receive data over the SPI port, and need some clarification on how to interpret the timing parameters.

In section 4.12.2 of the 6ULL Datasheet, Table 47 "ECSPI Master Mode Timing Parameters" has an SCLK cycle period of 43ns for a read, and 15ns for a write.

In Table 48 "ECSPI Slave Mode Timing Parameters" has an SCLK cycle period of 15ns for a read, and 43ns for a write.

15ns allows a ~66MHz max SCLK. 43ns allows a ~23MHz max SCLK. My application requires 26Mbps read into the 6ULL, so I need to confirm what the 6ULL is capable of. 

The relative direction of "read" and "write" is what's causing the confusion. In Table 48 (slave mode), do I interpret "read" as relative to the 6ULL, meaning 66MHz max clock when reading data into the device? Or is it relative to the master device, therefore SCLK is 23MHz when reading into the 6UL?

Also, how do these timings relate to the "52Mbps" specified in Table2?

Thanks.

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johnbaczewski
Contributor I

I likewise have the same question in relation to the i.MX6UL.

I suspect table 48 may has a typo.  I looked at the i.MX6DL datasheet and both Master and Slave have identical SCLK cycle period of 43ns for a read, and 15ns for a write.  If this is true then Read can never exceed 23 Mbps.

Jon Hallam - Did you ever get this tested?

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arnoutdiels
Contributor III

We ran into the same issue, not expecting the assymetry in the use of read/write.

60Mhz can only be achieved if MISO is not used.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  The i.MX6ULL Datasheet provides correct specs regarding eCSPI maximal frequency,

which is different for read and write ops. Read and write are considered relatively i.MX6ULL -

Your interpretation is correct.

   Also You may look at https://community.nxp.com/docs/DOC-95461 

Have a great day,
Yuri

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