I.MX7 power sequencing

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

I.MX7 power sequencing

846 次查看
NIKHITHAANTONY
Contributor I

In the datasheet of I.MX7 it is given that, VDD_SOC should powerup before NVCC_DRAM and NVCC_DRAM_CKE. So whether it can be done by software. In hardware design, whether we need to take care anything for delaying NVCC_DRAM and NVCC_DRAM_CKE

0 项奖励
回复
5 回复数

828 次查看
NIKHITHAANTONY
Contributor I

Then How VDD_SOC will become high before NVCC_DRAM and NVCC_DRAM_CKE.

0 项奖励
回复

822 次查看
igorpadykov
NXP Employee
NXP Employee

>How VDD_SOC will become high before NVCC_DRAM and NVCC_DRAM_CKE

 

in hardware. Use appropriate PMIC with power-up sequence compatible with i.MX7D datasheet

requirements.

 

Best regards
igor

0 项奖励
回复

814 次查看
NIKHITHAANTONY
Contributor I

We designed I.MX7 processor as per SABRE board. In that PMIC PF3000 is used. 

So there will be correct power sequencing..right?

0 项奖励
回复

809 次查看
igorpadykov
NXP Employee
NXP Employee

>We designed I.MX7 processor as per SABRE board. In that PMIC PF3000 is used. 

>So there will be correct power sequencing..right?

 

right

0 项奖励
回复

834 次查看
igorpadykov
NXP Employee
NXP Employee

Hi NIKHITHA

 

>whether it can be done by software..

 

no

 

>whether we need to take care anything for delaying NVCC_DRAM and NVCC_DRAM_CKE

 

no need.

 

Best regards
igor

0 项奖励
回复