we are planning to use NXP i.MX RT1176 together with multiple Micron NAND Flash MT29F256G08 (32 gigabytes, 2 LUNs per 1 CE) for raw data storage (not for bootloading).
It is not quite clear from the processor manual and from NAND flash SEMC source code example - how the SEMC controller needs to be configured to be able to switch between multiple memory modules and how the SEMC_CSX# processor pins should be connected.
Do I understand correctly that SEMC_CSX0 connects to the CE pin at Target1 and SEMC_CSX1 to the CE at Target2, etc.?
How is the target NAND Flash chip selected, does it need to be done with software or will the processor select the memory chip itself?
Where can I read in detail how the SEMC must be configured and how the memory modules must be connected to the CS pins on the board?
My apologies for the delay.
Yes, your understanding is correct, each of the chips would be connected to a Chip Select. SEMC_CSX0 connects to the CE pin at Target1 and SEMC_CSX1 to the CE at Target2.
You would need to setup the memory regions and the SEMC would be asserting the chip select depending on the region being accessed.
The processor reference manual can be a bit cumbersome but I would recommend looking at the SDK examples and the EVK for an example of how the SEMC works.
I hope that this information helps!