Hi Max,
From our HW engineer:
"There is no code for the test patterns. These are Built In Self Test (BIST) patterns contained in the PHY controller. You make the appropriate register setting (either through software, or manually through JTAG or a regisitry utility such as memtool) to SATA_BISTCR[TXO] and the PHY will output the selected, pre-programmed test pattern.
Other settings in the SATA_BISTCR register are used to set up the PHY to transmit the BIST pattern. The section you sited in the Reference Manual should be sufficient to guide you in using the BIST tests.
The SATA controller can initiate a BIST test on an attached device, or receive a command from an attached device to initiate a BIST test on its side, or can run a loop back BIST test. The Reference Manual describes how to do all three. Hopefully I have given you enough of a hint to use the Reference Manual. Please ask more specific questions if you have them."
Also, keep in mind that some BIST cannot be used after the IC is in a BGA package. This is described in the RM.
Hope this helps.
