How to Change Clock (CCM_CBCMR) in U-boot of i.MAX6Q ? ?

[peteramond]

Dear All,

The CCM_CBCMR register controls the clock source for the MMDC (memory controller) interfaces. The i.MX6 ROM configures this register so that the MMDC_CH0_CLK_ROOT and MMDC_CH1_CLK_ROOT clocks are sourced from the PLL2 main output (528 MHz). We can change these clocks to the PLL2-PFD2 output which runs at 396 MHz by adding the following lines into your DCD file in U-boot.

/* Configure MMDC clocks for 396 MHz operation */

DATA 4 0x020C4018 0x00260324

Hex 0x00260324 = Binary ‭0010 0110 0000 0011 0010 0100‬

1) To change MMDC_CH0_CLK_ROOT and MMDC_CH1_CLK_ROOT clocks which Bits should be changed from the following ? We can see with above hex settings; Are the only following bits will change above clock root clocks ?

Bit 21,22 = pre_periph2_clk_sel = PLL2_PFD2 = 396MHz  

Bit 18, 19 = pre_periph_clk_sel = PLL2_PFD2 = 396MHz

2) Don't we need to set  following bits to PLL2_PFD2 as well ?

Bit 16, 17 = gpu2d_core_clk_sel

Bit 15, 14 = vpu_axi_clk_sel

Bit 4, 5 = gpu3d_core_clk_sel

Register Name = CCM Bus Clock Multiplexer Register (CCM_CBCMR)

Address = 20C_4018

Regards,

Peter.

[igorpadykov]

Hi Peter

1. I think that using pre_periph2_clk_sel , pre_periph_clk_sel is correct.

Some examples can be found in SDK (core/src/ccm_pll.c)

Github SDK
https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK

Note if uboot is running from ddr, these modifications should be performed

running code from OCRAM.

2. if gpu,vpu are not used, no need to change these settings.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------