How do I safely disable unused PLLs on the iMX6SL

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How do I safely disable unused PLLs on the iMX6SL

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nathanpalmer
Contributor IV

I am trying to disable unused PLLs on an iMX6SL CPU.  The following code should:

  • Set the CPU Clock to 396MHz (From BareMetal SDK)
  • Configure clock defaults (From BareMetal SDK)
  • Disable 4 of the PLLs that (I think that) I am not using.  

This causes some weired behavior.  The code sometimes locks up after turning the PLLs off.  Am I missing something here?  I think that I have gated the proper clocks first.  Could the JTAG clock be affected by me disabling the PLLs?  Do I need some delay after disabling the PLLs?

Here is a snippit of code from my init function:

    // Use the SDK to set the root ARM clock PLL to 396MHz

    // Note: This calls pmu_init();

    int freq = cpu_workpoint_set(CPU_WORKPOINT_400MHZ);

    assert (freq != 0);

    /**

     * Configure Clocks

     */

    // First Initialize clock sources, dividers, with the SDK provided function

    ccm_init();

/**

* This code causes a fault that is not well understood!!!!

* If this code is executed then the code will jump in to the weeds.

* Not every time, but if the code is run and then stopped with the debugger 2 or 3 times then

* it will fail with PC = to some "random" location.

*/

#define DISABLE_PLLS

#ifdef  DISABLE_PLLS

    // Gate unused clocks to save power

    // Note that some clocks are gated here that will be turned on later via individual drivers

    HW_CCM_CCGR0_WR(0xffffffff);    // CPUDBG, AIPS

    HW_CCM_CCGR1_WR(0xf30C0f3f);    // GPU, GPT, ESAI, EPIT2/1, ECSPI4-1

    HW_CCM_CCGR2_WR(0xFFFFF03F);    // IPSYNC?, IPMUX, IOMUX, OCOTP, I2C3-1

    HW_CCM_CCGR3_WR(0xfffff000);    // OCRAM, MMDC, EPDC, LCDIF, PXP, CSI

    HW_CCM_CCGR4_WR(0x0000ffff);    // RAW NAND, PWM4-1, PL301?,

    HW_CCM_CCGR5_WR(0xf0030fcf);    // UART, SSI3-1, SPDIF, SPBA, SDMA, 100MHz, ROM CLK

    HW_CCM_CCGR6_WR(0xffff0c00);    // VPU, VDOA, EIM (SLOW), USDHC4-1, USB OH3

    // Disable unused PLLs after the downstream peripherals have been disabled

    // Note: The *_ENABLED bit should be left asserted even after the PLL is SHUTDOWN

    HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_BYPASS);        // Bypass the PLL

    HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_POWERDOWN);    // Power off the PLL

    HW_CCM_ANALOG_PLL_USB2_SET(BM_CCM_ANALOG_PLL_USB2_BYPASS);        // Bypass the PLL

    HW_CCM_ANALOG_PLL_USB2_CLR(BM_CCM_ANALOG_PLL_USB2_POWER);        // USB Uses a POWER bit instead of POWERDOWN

    HW_CCM_ANALOG_PLL_AUDIO_SET(BM_CCM_ANALOG_PLL_AUDIO_BYPASS);    // Bypass the PLL

    HW_CCM_ANALOG_PLL_AUDIO_SET(BM_CCM_ANALOG_PLL_AUDIO_POWERDOWN);    // Power off the PLL

    HW_CCM_ANALOG_PLL_VIDEO_SET(BM_CCM_ANALOG_PLL_VIDEO_BYPASS);    // Bypass the PLL

    HW_CCM_ANALOG_PLL_VIDEO_SET(BM_CCM_ANALOG_PLL_VIDEO_POWERDOWN);    // Power off the PLL

#endif

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igorpadykov
NXP Employee
NXP Employee

Hi Nathan

shortly:

set PMIC voltages

Configure IOMUX settings

Disable PLLs

Change CPU Speed

Initialize Clocks

then other

Best regards

chip

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igorpadykov
NXP Employee
NXP Employee

Hi Nathan

I would suggest to run tests from OCRAM

iRAM (OCRAM) i.MX6 SDK Application

and check if gated clock is used anywhere by other

module. When you access to module which clock is disabled,

application may hang. EB790 "Configuring PFDs" shows

how to enable/disable PFDs.

Best regards

chip

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nathanpalmer
Contributor IV

Thanks, I will try to run from OCRAM, however I hope that the final solution is one that does the configuration while running from SDRAM.

I have a related question about the order of operations while configuring the board.  If this grows into a seperate discussion I will create a new discussion page. I would like to do the following configurations at startup but I am having some bad behavior that may be related to the order that I am doing things.  This is the current order I am bringing up the board:

- Configure SDRAM (Done in OpenOCD init script and in U-Boot)

- Set-up C Environment (Done in Startup.s from Freescale SDK)

- Configure MMU/regions (from SDK, Page table in OCRAM)

- Enable Data and Instruction Cache

- Configure IOMUX settings

- Enable GIC Controller

- Change CPU Speed to 400MHz ( from SDK: cpu_workpoint_set(CPU_WORKPOINT_400MHZ) )

- Initialize Clocks ( ccm_init() )

- Disable PLLs (See first Post)

- Set PF0100 PMIC to SW1 = 0.95V ( This is NOT done for testing, so is not an issue for now)

- Configure the EIM interface for some on-board SRAM ( Not accessed for now, just want to get the order right )

... Start Program Code...

is there any issue with the order I am doing things?  For example. could the PLL problems be related to SLOW CPU Clock speed?  or Cache being enabled?  Is there a best practice for the order to configure Clocks/Memory/Cache/IOMUX/etc.

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igorpadykov
NXP Employee
NXP Employee

Hi Nathan

shortly:

set PMIC voltages

Configure IOMUX settings

Disable PLLs

Change CPU Speed

Initialize Clocks

then other

Best regards

chip

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1,338 Views
nathanpalmer
Contributor IV

When you suggest to set PMIC Voltages, is that internal or External or Both?   I am using Internal PMIC bypass, so I am turning the internal PMU full ON and configuring a PF0100 through I2C.  I am concerned that if I lower the PMIC voltage before changing the lowering the CPU speed then I will have a problem.   I assume that your flow assumes increasing the CPU speed and not decreasing it?

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igorpadykov
NXP Employee
NXP Employee

Yes, flow assumes increasing the CPU speed.

For decreasing flow first change CPU Speed then set PMIC voltages.

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