Gitter in pixel clock for VGA display in i.MX6 linux BSP

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Gitter in pixel clock for VGA display in i.MX6 linux BSP

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misbahkhan
Contributor II

Hello All,

We are using RGB to VGA display in our product with i.MX6

We have a VGA display and we are using linux 3.0.35 kernel

The issue that we are facing is that when the display's mode is set to 800*600 or

800*480 using the VESA timing parameters the pixel clock is set to 40Mhz

We can see that there is a gitter in the clock.

clk_set_parent(&ipu1_clk, &pll3_pfd_540M);

Can any one tell us why there is gitter when set to 40Mhz ?

40Mz is a standard clock that can be set, this is leading to the issue of picture on the display getting Blur effect.

This is very critical for us kindly help

Regards,

Misbah

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2 Replies

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Yuri
NXP TechSupport
NXP TechSupport

   Pixel IPU clock for Display has high jitter and does not have 50% duty cycle.

This is expected behavior, when the clock divider is set to a value that is not

an integer. When the divider is set to a non-integer value, the average frequency

of the clock will be correct, but the clock will jitter. Many displays works quite correctly

under non-50% duty cycle.

Rgards,

Yuri.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Misbah

one can observe jitter (or uneven periods) since 540Mhz

can not produce 40Mhz with even divider. So IPU will produce

correct 40Mhz frequency, however with jitter. For its removing one

can try to use other PLL/PFD as source with even divider for producing 40Mhz.

Best regards

igor

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