EIM bus access serialized across cores?

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EIM bus access serialized across cores?

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joshuaclayton
Contributor III

We have an application that uses the EIM bus to communicate with and FPGA.

There is an additional device connected to the FPGA, which communicates through the fpga by means of the EIM bus,

and has its own interrupts.

There is also a userspace program accessing registers via the EIM bus, which has been mmapped for direct access.

Thats a driver, two irqs, and a threaded application that may all be trying to read or write the EIM bus.

This was not my design, but I am wondering: does the IMX.6 serialize access to the EIM Bus, or do I have a race condition?

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506 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Joshua

EIM module is connected with AXI bus, allowing processing

one master at time, as described in IMX6DQRM  sect.22.1.1 Features:

ARM AXI slave interface. One ID at a time support.

Best regards

igor

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507 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Joshua

EIM module is connected with AXI bus, allowing processing

one master at time, as described in IMX6DQRM  sect.22.1.1 Features:

ARM AXI slave interface. One ID at a time support.

Best regards

igor

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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joshuaclayton
Contributor III

Thanks, Igor.

I could not have possibly comprehended the contents of the reference manual without knowing to go look up AXI in ARM documentation. Well, thats one less item to worry about.

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