EIM asynchronous mode showing multiple chip selects for single read

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

EIM asynchronous mode showing multiple chip selects for single read

Jump to solution
933 Views
varsmolta
Contributor V

I've ported over a simple kernel module from here (i.MX51 EIM bus clarified) and ported it to the imx6 and am doing a simple read of one address location on the EIM bus. When reading this one location, I get two chip select cycles going low, even though the data is only shown on the first chip select cycle. Why am I seeing two chip selects (and two Address strobe and two RWN cycles going low)? I don't see an example of this in any of the timing diagram.  Note: I am able to confirm that I can read what I have written so I think the bus is working in terms of data writes and reads. Its just the double chip select cycles going low that is bothering me.

P.S. In the screenshot MX6_DAT_IN(1) is really the EIM BCLK

eimCS0_debug.png

0 Kudos
Reply
1 Solution
722 Views
igorpadykov
NXP Employee
NXP Employee

Hi varsmolta,

this may be normal behaviour and related

to not -aligned access to WEIM from customer program.

In general you should always access to WEIM as to 32-bit peripheral

and with 32-bit aligned access. One can look at

Table 63-21 "WEIM Out/in Data in Case AXI Out/in Data is 0xB3B2B1B0"

i.MX51 Reference Manual (rev.1  2/2010)

http://www.freescale.com/files/dsp/doc/ref_manual/MCIMX51RM.pdf

Best regards

chip

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
Reply
1 Reply
723 Views
igorpadykov
NXP Employee
NXP Employee

Hi varsmolta,

this may be normal behaviour and related

to not -aligned access to WEIM from customer program.

In general you should always access to WEIM as to 32-bit peripheral

and with 32-bit aligned access. One can look at

Table 63-21 "WEIM Out/in Data in Case AXI Out/in Data is 0xB3B2B1B0"

i.MX51 Reference Manual (rev.1  2/2010)

http://www.freescale.com/files/dsp/doc/ref_manual/MCIMX51RM.pdf

Best regards

chip

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

0 Kudos
Reply