Direct MAC-MAC connection to Ethernet switch without a PHY

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Direct MAC-MAC connection to Ethernet switch without a PHY

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danielleloader
Contributor III

Hi iMX community.

We have a custom iMX6-based board which includes a Marvell 6350R switch. Our iMX6Q's Ethernet MAC is directly connected to the switch's port 5 MAC via RGMII with 6 nets in each direction: CLK, CTL and D[3:0]. (The switch only has PHYs on ports 0-4)

We have been unable to so far to use this interface in either U-Boot or Embedded Linux (Yocto build using fsl-community) despite the switch functioning: we can see it attempting to write packets to the iMX6 at 125MHz but receiving nothing back, not even at reset time. The switch's registers also report that the port is up and running at 125MHz RGMII.

I believe we have to use the FIXED_PHY configuration option and provide it with an initialisation structure to allow Linux to use the network interface. We have done this and added the following code to our board.c file in the Linux sources:

static struct fixed_phy_status phy_stat __initdata = {

.link   = 1,

.speed  = 1000,

.duplex = 0,

};

and in the board init function:

fixed_phy_add(PHY_POLL, 0, &phy_stat);

This compiles an runs, and in ifconfig we can now see eth0 with status of UP and reporting full duplex.

However, no matter what we do there is no activity from the iMX6 to the switch. DHCP requests and pings fail, and ifconfig never reports any activity at all, not even RX packets despite us being able to see them on scope.

We have also set (and confirmed by reading back) the following registers in the iMX6:

1) Analog ENET PLL Control Register: 0x80082003.

To generate 125MHz ENET clock. PLL lock bit goes high when we do this, so it's working.

2) IOMUXC_GPR1 ENET_CLK_SEL: 0x48642005

To use internal TX reference clock for ethernet (instead of a 125MHz input from a PHY)

3) Pad Group Control Register: 0x000C0000

IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII to set drive voltage correctly.                

And we have set the pin muxing for all these nets which we can again read back correctly. We can also access the switch over MDIO from U-Boot and Linux and toggle its reset state using a GPIO.

Is there something else we must do to enable Ethernet communication between these two devices?

Thanks

Dani

1 Solution
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jimmychan
NXP TechSupport
NXP TechSupport

Reply from the expert team:

Hi,

two things about this application:

1) you need to supply a 125MHz clock to ENET_REF_CLK

2) you cannot generate this clock using the output at GPIO_16 for this as it most likly has a pad that cannot support 125MHz. This works for fast ethernet

    with 25MHz, but almost certainly not with 125MHz for GMII. So get the 125MHz clock from the PHY and feed it into ENET_REF_CLK.

Greetings

Andreas

View solution in original post

12 Replies
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pinglisui
Contributor I

Hi, Danielle Loader,

     Now, I use the same scheme as yours. And now I met the same problem as yours. I am sure that my  ENET_REF_CLK pin has no problem. But I am not very  familiar with 88E6350R. Can you tell me the way you did in your u-boot and your Linux kernel? I wish you could give me some advices and share me your source code about this module in your u-boot and your linux kernel. My E-mail: suipingli@chinaxidian.com

     Thank you!

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alexwang
Contributor II

Hi experts,

I have the same problem of MAC to MAC connection between i.MX6 and RTL8364 switch.

The nets connection are correct and ENET_REF_CLK is connected to 125MHz Oscillator.

In our Android software setting only has AR8031 PHY driver, we don't know how to make i.MX6 work with RTL8364 switch.

Could you help us?

Thank you.

B/R

Rich

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alexwang
Contributor II

Hi, expert,

Since this community thread is closed.

I post a new one here. i.MX6 GMAC to GMAC connection

Thank you.

B/R

Rich

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successansucces
Contributor I

HI Danielle, I have the same connecting as follow.

i.MX6               Switch

--------               ----------

TXD[3:0]---------RXD[3:0]

TX_CTL----------RX_CTL

GTX_CLK-------RX_CLK

RXD[3:0]---------TXD[3:0]

RX_CTL----------TX_CTL

RX_CLK----------GTX_CLK

*ENET_REF_CLK connected to external 125MHz source

But IMX6Q haven't 125MHz GTX_CLK and data output yet. Switch can output 125MHz GTX_CLK and data normally.

Can you tell me how to modify the driver and give me the step or notes?  Now I haven't  any ideal for this question?

I beg your reply. Thank you very much!

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jaredl
Contributor I

I am struggling with an RGMII MAC to MAC connection on my board similar to what you describe (RGMII port on i.MX6 connected directly to RGMII on a switch).  If you got this to work, will you please post a diagram of the signal connections between the two chips?  I am looking for something like the following:

i.MX6               Switch

--------               ----------

TXD[3:0]---------RXD[3:0]

TX_CTL----------RX_CTL

GTX_CLK-------RX_CLK

and so forth...

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danielleloader
Contributor III

Hi Jaredl

We have those 6 connections, plus a 125MHz TX_CLK from a spare port on our switch that goes into ENET_REF_CLK - that is what prevented this from working for us. Now that we are supplying the clock it seems to be working fine.

Dani

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jaredl
Contributor I

Dani,

Thanks!  I really appreciate the response.  It is very helpful to hear that you got this working.  I have found various information about making this type of connection, but you are the first to confirm that it actually worked.

We have all 6 connections along with an external 125MHz clock feeding the ENET_REF_CLK pin on the i.MX6, so we must be having a different issue.  We are using a different switch (BCM89501 from Broadcomm).  Did you have to do any special configuration to your Marvell switch to get it to support the MAC to MAC connection?

Below is a full list of our connections for anyone who comes across this in the future (I also edited the previous post to label the GTX_CLK properly).

i.MX6               Switch

--------               ----------

TXD[3:0]---------RXD[3:0]

TX_CTL----------RX_CTL

GTX_CLK-------RX_CLK

RXD[3:0]---------TXD[3:0]

RX_CTL----------TX_CTL

RX_CLK----------GTX_CLK

*ENET_REF_CLK connected to external 125MHz source

NOTE:  The i.MX6 connections are the RGMII_TXD[3:0], RGMII_TX_CTL, RGMII_TXC, RGMII_RXD[3:0], RGMII_RX_CTL, RGMII_RXC signals.

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shabeerbadarudh
Contributor IV

Hi Jardel,

We are going to integrate BCM89501 to i.MX6 host. Could you help us about software configuration.

1. Any Linux drivers/Device tree details  are available for BCM89501.

2. How do we test this switch in Linux Userspace.

3. Any useful links / documents are available.

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jimmychan
NXP TechSupport
NXP TechSupport

Reply from the expert team:

Hi,

two things about this application:

1) you need to supply a 125MHz clock to ENET_REF_CLK

2) you cannot generate this clock using the output at GPIO_16 for this as it most likly has a pad that cannot support 125MHz. This works for fast ethernet

    with 25MHz, but almost certainly not with 125MHz for GMII. So get the 125MHz clock from the PHY and feed it into ENET_REF_CLK.

Greetings

Andreas

View solution in original post

3,622 Views
staaleaakermann
Contributor I

Hi.

We have the same issue regarding interfacing a Marvell 6350R switch directly to the imx6q MAC. Before we make a new layout, I'm wondering if its possible to MUX the RGMII_RXC with the ENET_REF_CLK? I'm also curious why the ENET_REF_CLK is required when its possible to have ENET_PLL running at 125Mhz.

Best Regards

Staale Aakermann

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danielleloader
Contributor III

Hi Jimmy,

We are currently respinning our PCB to add this clock and I will reply with the results.

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YixingKong
Senior Contributor IV

Danielle, we will close the DI for now. If you have any questions, please come to here to create a new discussion.

Thanks,

Yixing

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