Difference between watchdog reset and chip reset in MX25.

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Difference between watchdog reset and chip reset in MX25.

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george
Senior Contributor II

Dear all,

I have received the question from my customer about the difference in chip initialization by two reset sources.

A) By external input pin RESET_B
B) By timeout of Inside Watchdog-timer

I read the reference manual and the datasheet, in order to know to the difference.

But these seem not to be clear.

Where should I see about it?

Best Regards,

George

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Yuri
NXP Employee
NXP Employee

Hello,

  Please look at Table 6-2 (Reset Sources and Qualification Conditions) of the

i.MX25 Reference Manual. General considerations regarding reset specifics are as
following :

  There are 3 types of resets on i.MX25. A POR reset, cold reset, and warm reset.

Both POR_B and RESET_B reset are reset sources for i.MX25.

  A POR reset will reset the entire i.MX25 including any register settings, external memory

interface configuration etc. The only thing that will not be reset is the RTC if maintaining RTC with

battery. Only way to reset RTC in this case is with SW interaction to DRYICE module.

  A Cold reset resets entire i.MX25 except for test/debug blocks such as SJC, ETM, ECT. 

This reset state exists for debugging purposes. A Cold reset is qualified after RESET_B is asserted

for a duration greater than 5 seconds on the RESET_B pin.

  A Warm reset resets entire i.MX25 except for EMI, SDRAMC. The NFC and WEIM will be reset. This reset

will reset i.MX25 while keeping the external memory configuration to SDRAM. A Warm reset is qualified when

RESET_B is asserted for a duration less than 5 seconds on the RESET_B pin, OR a reset signal is asserted

on the JTAG connector, OR a software reset is initialized from JATAG reset, OR a reset is asserted from the

WDOG module, OR a software initialized reset from the ARM core. 

  Watchdog (internally) provides warm reset.

Have a great day,
Yuri

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Yuri
NXP Employee
NXP Employee

Hello,

  Please look at Table 6-2 (Reset Sources and Qualification Conditions) of the

i.MX25 Reference Manual. General considerations regarding reset specifics are as
following :

  There are 3 types of resets on i.MX25. A POR reset, cold reset, and warm reset.

Both POR_B and RESET_B reset are reset sources for i.MX25.

  A POR reset will reset the entire i.MX25 including any register settings, external memory

interface configuration etc. The only thing that will not be reset is the RTC if maintaining RTC with

battery. Only way to reset RTC in this case is with SW interaction to DRYICE module.

  A Cold reset resets entire i.MX25 except for test/debug blocks such as SJC, ETM, ECT. 

This reset state exists for debugging purposes. A Cold reset is qualified after RESET_B is asserted

for a duration greater than 5 seconds on the RESET_B pin.

  A Warm reset resets entire i.MX25 except for EMI, SDRAMC. The NFC and WEIM will be reset. This reset

will reset i.MX25 while keeping the external memory configuration to SDRAM. A Warm reset is qualified when

RESET_B is asserted for a duration less than 5 seconds on the RESET_B pin, OR a reset signal is asserted

on the JTAG connector, OR a software reset is initialized from JATAG reset, OR a reset is asserted from the

WDOG module, OR a software initialized reset from the ARM core. 

  Watchdog (internally) provides warm reset.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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george
Senior Contributor II

Dear Yuri,

Thank you for the reply.

I was not able to find it.

Thnaks,

George

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