DDR configurations for iMX8M Plus

[xueyf]

Hi,

I am planning to use Nanya DDR part NT6AN512T32AV with iMx8m plus processor. I have filled the XLS sheet MX8M_Plus_LPDDR4_RPA_v9.xlsx with required details. Can anyone review the configuration and confirm if the filled details are correct.

[Dhruvit]

Hi @xueyf,

I hope you are doing well.

The below-mentioned parameter needs to be changed in the RPA file for NT6AN512T32AV part.

Density per channel per chip select (Gb)1: 16

Please change Density per channel per chip select to 8Gb.

NT6AN512T32AV is a dual channel DRAM (8 Gb density per channel)

Thanks & Regards,
Dhruvit Vasavada.

[xueyf]

Thank you for your response.

However, when I press the calibration button, the interface keeps getting stuck at STEP 1. What should I do to resolve this issue?

[Dhruvit]

Hi @xueyf,

I hope you are doing well.

From the RPA file, It seems that the DDR clock frequency is changed from the default configuration.

Please note that RPA file only supports 1500Mhz and 2000Mhz clock frequency 

For frequencies other than these two, it is up to the user to create the appropriate register setting for the desired frequency. (DRAM_PLL_FDIV_CTL0 ).

Please refer to the below document for more information.

iMX 8M Mini Register Programming Aid DRAM PLL setting

Thanks & Regards,
Dhruvit Vasavada

[xueyf · Accepted solution]

You're welcome!

I have completed the calibration, but I'm experiencing abnormal behavior with the network interface after calibration.

How can I resolve this issue?

[xueyf]

I'm glad to hear that the issue has been resolved!