Hello,
Please look at my comments below.
1.
Look at section 35.12.9 [MMDC Core Refresh Control Register (MMDC_MDREF)] of i.MX 6ULL
Reference Manual, Rev. 1, 11/2017, regarding refresh control.
2.
Mode Register 2 (MR2) contains bit ASR. MR registers usually configured during memory
initialization.
3.
Yes, it is reasonable to double the refresh rate at high temperature.
Have a great day,
Yuri
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