Can anybody explain me the contains of linux file arch/arm/boot/dts/imx6q-pinfunc.h.

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Can anybody explain me the contains of linux file arch/arm/boot/dts/imx6q-pinfunc.h.

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embedded_ashu
Contributor II

Hi All,

I am quite new to device tree i go through the imx6 linux BSP.

In file arch/arm/boot/dts/imx6q-pinfunc.h

I find some defination such as:

#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x244 0x62c 0x000 0x4 0x0

mux_reg      0x244

conf_reg      0x62c

input_reg      0x000

mux_mode     0x4

input_val      0x0

But where to find this values in Datasheet. I am only able to find mux mode in Chapter 38 IOMUX Controller (IOMUXC)

38.3.127 SW_MUX_CTL(IOMUXC_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0)

What about the rest. please help me out.

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1 Solution
2,115 Views
embedded_ashu
Contributor II

********************************************************************************************************

vi arch/arm/boot/dts/imx6qdl.dtsi +1102


uart4 {

                                        pinctrl_uart4_1: uart4grp-1 {

                                                fsl,pins = <

                                                        MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1

                                                        MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1

                                                >;

                                        };

                                };


********************************************************************************************************

vi arch/arm/boot/dts/imx6q-pinfunc.h +578


#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x1f8 0x5c8 0x000 0x4 0x0

#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA          0x1fc 0x5cc 0x938 0x4 0x1


********************************************************************************************************

UART4_TX

mux_reg = 0x1f8   0x1f8 is offset of KEY_COL0’s MUX setting


36.4.122 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL0)

Address: 20E_0000h base + 1F8h offset = 20E_01F8h


UART4_RX

mux_reg = 0x1fC   0x1fC is offset of KEY_ROW0’s MUX setting


36.4.123 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0)

Address: 20E_0000h base + 1FCh offset = 20E_01FCh

********************************************************************************************************


UART4_TX

conf_reg = 0x5C8 0x5C8 is offset of KEY_COL0’s PAD setting,


36.4.366 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL0)

Address: 20E_0000h base + 5C8h offset = 20E_05C8h

MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1


UART4_RX

conf_reg = 0x5CC 0x5CC is offset of KEY_ROW0’s PAD setting,


36.4.367 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0)

Address: 20E_0000h base + 5CCh offset = 20E_05CCh


MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1

MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1


16 15 14 13 12 11 10 9 8 7 6 5 4

1 1 0 1 1 0 0 0 0 1 0 1 1


3 2 1  0

0 0 0 1


For Both UART4 -Tx & Rx same configuration







********************************************************************************************************

UART4 Tx

input_reg = 0x000

Input_reg 0x000 means setting this KEY_COL0 pin to work as UART4_TX_DATA, no need to set daisy chain(select input). If setting to UART4_RX_DATA, then need to set daisy chain, see detail in IOMUXC chapter in RM,IOMUXC_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0, Config Register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode ALT4.

UART4 Rx

input_reg = 0x938

36.4.585 Select Input Register (IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT)

Address: 20E_0000h base + 938h offset = 20E_0938h


********************************************************************************************************

UART4 Tx

mux_mode = 0x4 0x4 means set to mux mode 4, UART4_TX


UART4 Rx

mux_mode = 0x4 0x4 means set to mux mode 4, UART4_RX


********************************************************************************************************

UART4 Tx

input_val = 0x0


UART4 Rx

input_val = 0x1


IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT field descriptions

1–0

DAISY

00 KEY_COL0_ALT4 — Selecting ALT4 mode of pad KEY_COL0 for UART4_TX_DATA.

01 KEY_ROW0_ALT4 — Selecting ALT4 mode of pad KEY_ROW0 for UART4_RX_DATA.

********************************************************************************************************


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3 Replies
2,116 Views
embedded_ashu
Contributor II

********************************************************************************************************

vi arch/arm/boot/dts/imx6qdl.dtsi +1102


uart4 {

                                        pinctrl_uart4_1: uart4grp-1 {

                                                fsl,pins = <

                                                        MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1

                                                        MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1

                                                >;

                                        };

                                };


********************************************************************************************************

vi arch/arm/boot/dts/imx6q-pinfunc.h +578


#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x1f8 0x5c8 0x000 0x4 0x0

#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA          0x1fc 0x5cc 0x938 0x4 0x1


********************************************************************************************************

UART4_TX

mux_reg = 0x1f8   0x1f8 is offset of KEY_COL0’s MUX setting


36.4.122 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL0)

Address: 20E_0000h base + 1F8h offset = 20E_01F8h


UART4_RX

mux_reg = 0x1fC   0x1fC is offset of KEY_ROW0’s MUX setting


36.4.123 Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0)

Address: 20E_0000h base + 1FCh offset = 20E_01FCh

********************************************************************************************************


UART4_TX

conf_reg = 0x5C8 0x5C8 is offset of KEY_COL0’s PAD setting,


36.4.366 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL0)

Address: 20E_0000h base + 5C8h offset = 20E_05C8h

MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1


UART4_RX

conf_reg = 0x5CC 0x5CC is offset of KEY_ROW0’s PAD setting,


36.4.367 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0)

Address: 20E_0000h base + 5CCh offset = 20E_05CCh


MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1

MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1


16 15 14 13 12 11 10 9 8 7 6 5 4

1 1 0 1 1 0 0 0 0 1 0 1 1


3 2 1  0

0 0 0 1


For Both UART4 -Tx & Rx same configuration







********************************************************************************************************

UART4 Tx

input_reg = 0x000

Input_reg 0x000 means setting this KEY_COL0 pin to work as UART4_TX_DATA, no need to set daisy chain(select input). If setting to UART4_RX_DATA, then need to set daisy chain, see detail in IOMUXC chapter in RM,IOMUXC_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0, Config Register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode ALT4.

UART4 Rx

input_reg = 0x938

36.4.585 Select Input Register (IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT)

Address: 20E_0000h base + 938h offset = 20E_0938h


********************************************************************************************************

UART4 Tx

mux_mode = 0x4 0x4 means set to mux mode 4, UART4_TX


UART4 Rx

mux_mode = 0x4 0x4 means set to mux mode 4, UART4_RX


********************************************************************************************************

UART4 Tx

input_val = 0x0


UART4 Rx

input_val = 0x1


IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT field descriptions

1–0

DAISY

00 KEY_COL0_ALT4 — Selecting ALT4 mode of pad KEY_COL0 for UART4_TX_DATA.

01 KEY_ROW0_ALT4 — Selecting ALT4 mode of pad KEY_ROW0 for UART4_RX_DATA.

********************************************************************************************************


2,114 Views
alejandrolozan1
NXP Employee
NXP Employee

Hi Ashutosh,

I wonder if you could clarify this doubt. It seems that you did but if I am wrong please let us know.

Best Regards,

Alejandro

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2,115 Views
embedded_ashu
Contributor II

Hi Alejandro,

I posted this question on the forum but did not get any reply so i tried by my self and got a conclusion and then replied the same, so that if anybody have the same question they have the answer. Is my understanding is correct or some where i am wrong.

Regard

Ashutosh Singh

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