Big / Little Endian mode (i.MX6Q SDP)

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Big / Little Endian mode (i.MX6Q SDP)

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jotes
Contributor IV

Hello everyone!

In i.MX 6Dual/6Quad Applications Processor Reference Manual I have found:

"i.MX 6Dual/6Quad supports Little Endian mode only."

as well as:

"The Cortex-A9 Core Platform supports little endian mode only. Big Endian is not

supported even though both modes are supported by the Cortex-A9 processor."

What does it mean in practice? Does it mean that i can't manually change endianness by "SETEND" command?

But when I try this code:

*(unsigned long *) 0x20000100 = 0;

*(unsigned long *) 0x20000200 = 0;

__asm volatile ("SETEND LE \n\t");

(*(unsigned long *) 0x20000100)++;

__asm volatile ("SETEND BE \n\t");

(*(unsigned long *) 0x20000200)++;

it seems that everything is ok (I mean value at 0x20000100 is in Little Endian mode and value at 0x20000200 is in Big Endian mode):

0x20000100:  00000001

0x20000200:  01000000

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AnsonHuang
NXP Employee
NXP Employee

Hi, jotes

     I saw this from RM:

Peripherals always assume little-endian-aligned data arrives or

departs on their 32-bit APB.

     So, maybe ARM core support both big and little ending, but the peripherals only support little ending.

在原帖中查看解决方案

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niklasmolin
Senior Contributor I

I saw in document IMX6DQRM, section 1.5.3.

"i.MX 6Dual/6Quad supports Little Endian mode only."

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Yuri
NXP Employee
NXP Employee

Yongcai Huang is right - the problem relates to internal peripheral modules / controllers of the i.MX6.
The ARM core can be configured for Little or Big endian, but this means all data, passing through core
will be affected. Users often need to use different endian modes for different modules. Such configuration
is hard to support.   

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AnsonHuang
NXP Employee
NXP Employee

Hi, jotes

     I saw this from RM:

Peripherals always assume little-endian-aligned data arrives or

departs on their 32-bit APB.

     So, maybe ARM core support both big and little ending, but the peripherals only support little ending.

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