Access to watchdog in imx8qxp

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Access to watchdog in imx8qxp

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fx73
Contributor I

SCFW appears to contain hw-level abstraction, but then there's also the Arm Trusted Firmware, which appears to require assembly code to clear/kick/ping the watchdog by writing 0xc2000002 with 0x04 to the x0 and x1 registers.

If the arm trusted firmware provides an exception to allow the SCFW to access the watchdog ping, start, stop, etc., why do code examples appear to just write the x-reg's directly rather than going through the SCFW calls? This relationship is not fully clear.

As far as the watchdog is concerned, is the arm trusted firmware smc calls mutually exclusive to the SCFW?

I realize writing via mmap is no longer possible, but, Is it at all possible for an application to somehow still read Watchdog Control and Status Register (CS)?

 

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jimmychan
NXP TechSupport
NXP TechSupport

Hello,

 

I got the reply from the expert

====================

There is no hardware watchdog for the Linux partition - instead it is a virtual/software watchdog maintained by the SCFW. To refresh the WDOG, Linux must make an SMC call to ATF because it has one side of the MU connected to the SCFW so it can communicate and ping the watchdog. After the SMC call to ATF has been made ATF will then utilize the SCFW API to refresh the virtual watchdog.

====================

 

Best regards,

Jimmy

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fx73
Contributor I

What about getting the status? 

It appears there are 5 register values, of which:

  • arg0  = IMX_FSL_SIP_SRTC
  • arg1  =  IMX_FSL_SIP_SRTC_GET_WDOG_STAT
  • arg2  = ?
  • arg3  = ?
  • arg4  = ?

The return value is always zero and all arg's are type uint64 and not pointers, which doesn't leave any other options unless the function itself is different for a "GET". The only smc call I see is:

Also, is there a document which specifies which registers map to which for smc calls?

static inline imx_smc_status_t imx_smc_call_psci(
    uint64_t reg0, uint64_t reg1, uint64_t reg2, uint64_t reg3, uint64_t reg4)
{
    __asm__ __volatile__(
        "ldr x0, %0\n"
        "ldr x1, %1\n"
        "ldr x2, %2\n"
        "ldr x3, %3\n"
        "ldr x4, %4\n"
        "smc    #0\n"
        "str x0, %0\n"
        : "+m"(reg0), "+m"(reg1),
        "+m"(reg2), "+m"(reg3), "+m"(reg4)

        : "m"(reg0)
        : "x0", "x1", "x2", "x3", "x4"
    );
    return reg0;
}

 

Reference:

#define IMX_FSL_SIP_SRTC 0xC2000002
#define IMX_FSL_SIP_SRTC_SET_TIME 0x00
#define IMX_FSL_SIP_SRTC_START_WDOG 0x01
#define IMX_FSL_SIP_SRTC_STOP_WDOG 0x02
#define IMX_FSL_SIP_SRTC_SET_WDOG_ACT 0x03
#define IMX_FSL_SIP_SRTC_PING_WDOG 0x04
#define IMX_FSL_SIP_SRTC_SET_TIMEOUT_WDOG 0x05
#define IMX_FSL_SIP_SRTC_GET_WDOG_STAT 0x06
#define IMX_FSL_SIP_SRTC_SET_PRETIME_WDOG 0x07

 

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