About i.MX6 ULL DDR3.

[ryoichiyokota]

I want to know DDR3 max density.

Please teach me.

Best regards.

[igorpadykov]

Hi ryoichi

max. density is defined by max. row=16, col=12 settings in MDCTL register

described in sect.36.12.1 MMDC Core Control Register (MMDC_MDCTL) i.MX6ULL RM

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULLRM.pdf 

Best regards
igor
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