Hello,
MIPI-CSI2 has STREAM_FENCING_CONTROL register. I have checked following VC enabling patch.
It seems like the STREAM_FENCING_CONTROL register is not using by linux BSP.
Could you please explain me feature of STREAM_FENCING_CONTROL register?
What does "Fence VC0" mean?
ISL79987 and adv7180 de-interlace driver for iMX8QXP boards
From IMX8DQXPRM.pdf (Rev.0)
Best Regards,
Kazuma Sasaki.
解決済! 解決策の投稿を見る。
Hi Kazuma Sasaki
The stream_fencing is used to tell the MIPI CSI2 stop data transfer to pixel link.
For example, software can write "Fence VC0" to STREAM_FENCING_CONTROL register, then after MIPI CSI2 stops to transfer VC0 data to pixel link, the status "VC0 is fenced" can be read from STREAM_FENCING_STATUS register.
MIPI CSI2 reset can recover it.
Have a nice day
Best Regards,
Rita
Hi Kazuma Sasaki
The stream_fencing is used to tell the MIPI CSI2 stop data transfer to pixel link.
For example, software can write "Fence VC0" to STREAM_FENCING_CONTROL register, then after MIPI CSI2 stops to transfer VC0 data to pixel link, the status "VC0 is fenced" can be read from STREAM_FENCING_STATUS register.
MIPI CSI2 reset can recover it.
Have a nice day
Best Regards,
Rita
Dear Rita Wang,
I appreciate your support. I got it.
Best Regards,
Kazuma Sasaki.