3.3V LDO unstable in few custom i.MX25 boards.

[torus1000]

Hi,

The following power-up sequence is recommended for i.MX25.

  1. Assert power on reset (POR).

  2. Turn on digital logic domain and I/O power supplies VDDn and NVCCx.

  3. Turn on all other analog power supplies

  4. Negate the POR signal

So our board designed as following.

(0) POR=L (1) LDO_1.2V on (2) LDO_3.3V on (3) LDO_1.8V on (4) POR release

Most boards(90%) started up with no problem and stable but rest of boards(10%) looked unstable.

Please see attached waveforms.

LDO_1.2V (ch1: yellow) rise first then LDO_3.3V (ch2: cyan) rise next but oscillation waveform observed.

(Additionally saying, this oscillation seems suppressed if add delay to the enable pin of LDO_3.3V.)

Why this type of oscillation happened in few specific boards?

How can I fix it? Is there any hardware design guide documents?

Can anyone help me?

Thanks.

[art · Accepted solution]

According to the oscilloscope curves you've provided, seems that the digital I/O supply voltage (3.3V) starts its ramp-up before the core supply voltage (1.2V) becomes stable that causes the current leakage and latch-up effect between the power domains. To eliminate the effect, try to add more delay between 1.2V and 3.3V supplies ramp-up start.

Have a great day,
Artur

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