In my RGMII setup i would like to remove the PHY crystal so i'm hoping to generate 25 MHz (instead of 50 MHz for RMII use cases) from GPIO16, route it to the PHY and then route back the 125MHz clock from this to the ENET_REF_CLK. Does this setup work?
If not, are there any other suitable I/Os to generate a 25MHz clock available?