In my RGMII setup i would like to remove the PHY crystal so i'm hoping to generate 25 MHz (instead of 50 MHz for RMII use cases) from GPIO16, route it to the PHY and then route back the 125MHz clock from this to the ENET_REF_CLK. Does this setup work?
If not, are there any other suitable I/Os to generate a 25MHz clock available?
Hello Langer Boris,
It is possible to do as you wish, as mentioned on Table 2-9 of the Hardware Development Guide for i.MX6 (link below).
http://www.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf
You may either generate the 125MHZ but if your PHY requires the 25MHZ you may configure the clock to feed the PHY and then bring the 125MHZ clock to ENET_REF_CLK.
I hope this helps!
Regards,