i.MX7D DRAM Register Programming Aids

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i.MX7D DRAM Register Programming Aids

i.MX7D DRAM Register Programming Aids

Important: If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the i.MX community. Please note that any private messages or direct emails are not monitored and will not receive a response.

These are detailed programming aids for the registers associated with DRAM initialization (LPDDR3, DDR3, and LPDDR2). The last work sheet tab in the tool formats the register settings for use with the ARM DS5 debugger. It can also be used with the windows executable for the DDR Stress Test (note the removal of debugger specific commands in this tab). These programming aids were developed for internal NXP validation boards.


This tool serves as an aid to assist with programming the DDR interface of the MX7D and is based on the DDR initialization scripts developed for NXP boards and no guarantees are made by this tool.


The following are some general notes regarding this tool:

  • The default configuration for the tool is to enable bank interleaving.
  • Refer to the "How To Use" tab in the tool as a starting point to use this tool.
  • The tool can be configured for one of the three memory types supported by the MX7D.  However, three separate programming aids are provided based on the DRAM type: LPDDR3, LPDDR2, and DDR3.  Therefore, you may use the tool pre-configured for your desired memory type as a starting point.
  • The DRAM controller IP in MX7D is different from the MX6 series MMDC controller. Results from DRAM calibration may be updated for the following registers: DDR_PHY_OFFSET_WR_CON0 (0x30790030) and DDR_PHY_OFFSET_RD_CON0 (0x30790020).  Also, the MX7D memory map DRAM starting address is fixed at 0x80000000.
  • Some of the CCM programming at the beginning of the DRAM initialization script (in the "DStream .ds file" tab) were automatically generated and in very few cases may involve writing to reserved bits, however, these writes to reserved bits are simply ignored.
  • Note that in the "DStream .ds file" tab there are DS5 debugger specific commands that should be commented out or removed when using the DRAM initialization for non-debugger specific applications (like when porting to bootloaders).
  • This tool may be updated on an as-needed basis for bug fixes or future improvements.  There is no schedule for aforementioned maintenance.
  • For questions or additional assistance using this tool, please contact your local sales or FAE.
Labels (2)

Hello Michael,

One ZQ cali related bug had been idendified, please refer to thread.i.MX7 : ZQ calibration sequence is inconsistent with reference manual

Update programming aid will be appreciated.

Hi LinWang,

Thank you for bringing this to my attention.  I have made the necessary changes per the thread you referenced.



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Last update:
‎05-03-2021 02:18 PM
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