DDR_Stress_Tester is a software application for fine tuning DDR parameters and verifying DDR
performance on i.MX6 boards. It performs write leveling, DQS gating, read/write delay
calibration on the target board to match the layout of the board and archive the best DDR performance.
In addition, the stress test can help the user to verify the DDR performance on their boards.
The following are the features supported:
• Support i.MX6Q, i.MX6D, i.MX6DL, iMX6S, i.MX6SL, and i.MX6SX DDR calibration.
• Support DDR3 write leveling, DQS gating, Read/Write Delay auto-calibration.
• Support LPDDR2 Read/Write Delay auto-calibration.
• Support 16 bits, 32 bits, and 64 bits data bus.
• Support fixed-mapping 2-channel LPDDR2.
• Support DDR stress test between the frequency 135MHz and 672 MHz
If USB OTG port is not available on customer board, please use the images in DDR_Stress_Tester_V1.0.3_UART1_for_SDboot&JTAG.zip.
The bin files in the packages can be loaded by uboot and elf files are used by JTAG load. Please note when the image is loaded by u-boot, the DDR is initialized by u-boot (reference flash_header.S).
To run ddr stress test from u-boot, CONFIG_SPLASH_SCREEN must be disabled in u-boot. Because when enter self refresh mode in ddr stress test, DRAM access will be blocked. If splash screen in u-boot is enabled, IPU will continuously access DRAM, so the system will hang up.
If you have other DMA access in u-boot, it must be disabled.
If customer uses different RX/TX pin for UART, please contact FAE.