The purpose of this document is to specify the maximum LPDDR4 ,DDR4 and DDR3L densities that are supported by i.MX 8M family of processors to aid project feasibility assessment capabilities of customers that are evaluating the SoCs for usage in their products.
It is strongly recommended to consult with NXP and the memory vendor the final choice of the memory part number to ensure that the device meets all the compatibility, availability, longevity and pricing requirements.
In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs.
For any questions related to specific DRAM part numbers please contact the respective DRAM vendor. For any questions regarding the i.MX SoC please contact your support representative or enter a support ticket.
LPDDR4
SoC  Max data bus width  Maximum density  Assumed memory organization  Notes 
i.MX 8M Quad  32bit  32Gb/4GB  dual rank, dualchannel device with 16row addresses (R0R15)  1, 2, 4 
i.MX 8M Mini  32bit  64Gb/8GB  dual rank, dualchannel device with 17row addresses (R0R16)  1, 2 
i.MX 8M Nano  16bit  32Gb/4GB  dual rank, singlechannel device with 17row addresses (R0R16)  1, 2, 3, 12 
i.MX 8M Plus  32bit  64Gb/8GB  dual rank, dualchannel device with 17row addresses (R0R16)  1, 2 
LPDDR4  list of validated memories
The validation process is an ongoing effort  regular updates of the table are expected.
SoC  Density  Validated part number (vendor)  Notes 
i.MX 8M Quad  24Gb/3GB 
MT53B768M32D4NQ062 WT:B (Micron) 
 
i.MX 8M Mini 
16Gb/2GB 
MT53D512M32D2DS053 WT:D (Micron) 
 
16Gb/2GB 
M56Z16G32512A (ESMT) 
5 

32Gb/4GB 
MT53E1G32D2FW046 WT:A (Micron) 
5 

64Gb/8GB 
MT53E2G32D4DT046 AIT:A (Micron) 
5 

i.MX 8M Nano 
16Gb/2GB  C1612PC2WDGTKRU (Kingston)   
32Gb/4GB 
MT53E2G32D4DT046 AIT:A (Micron) 
5, 13  
8Gb/1GB  MT53D512M32D2DS053 WT:D (Micron)  13  
i.MX 8M Plus  48Gb/6GB 
MT53E1536M32D4DT046 WT:A (Micron) 
 
DDR4
SoC  Max data bus width  Maximum density  Assumed memory organization  Notes 
i.MX 8M Quad  32bit  32Gb/4GB  x16, 16Gb device with 1 bank group address, 17row addresses and 10 column addresses  1, 6 
i.MX 8M Mini  32bit  64Gb/8GB  x16, 16Gb device with 1 bank group address, 17row addresses and 10 column addresses  1, 7 
i.MX 8M Nano  16bit  64Gb/8GB  x8, 16Gb device with 2 bank group addresses, 17row addresses and 10 column addresses  1, 8 
i.MX 8M Plus  32bit  64Gb/8GB  x16, 16Gb device with 1 bank group address, 17row addresses and 10 column addresses  1, 7 
DDR4  list of validated memories
The validation process is an ongoing effort  regular updates of the table are expected.
SoC  Density  Validated part number (vendor) 
i.MX 8M Quad  32Gb/4GB 
4x MT40A512M16JY083EAAT (Micron) 
i.MX 8M Mini  16Gb/2GB  2x MT40A512M16LY075:E (Micron) 
i.MX 8M Nano  16Gb/2GB  1x MT40A1G16RC062E:B (Micron) 
i.MX 8M Plus 
64Gb/8GB  4x MT40A1G16RC062E:B (Micron) 
16Gb/2GB  NT5AD512M16C4JRI (Nanya) 
DDR3L
SoC  Max data bus width  Maximum density  Assumed memory organization  Notes 
i.MX 8M Quad  32bit  32Gb/4GB  x16, 8Gb device with 16row addresses and 10 column addresses  1, 9 
i.MX 8M Mini  32bit  64Gb/8GB  x8, 8Gb device with 16row addresses and 11 column addresses  1, 10 
i.MX 8M Nano  16bit  32Gb/4GB  x8, 8Gb device with 16row addresses and 11 column addresses 
1, 11 
i.MX 8M Plus 
i.MX 8M Plus does not support DDR3L 
DDR3L  list of validated memories
The validation process is an ongoing effort  regular updates of the table are expected.
SoC  Density  Validated part number (vendor) 
i.MX 8M Quad  16Gb/2GB  4x MT41K256M16TW107 AAT (Micron) 
i.MX 8M Mini  16Gb/2GB  4x MT41K256M16TW107 AAT (Micron) 
Note 1:
The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, and on the JEDEC standards JESD2094/JESD2094A (LPDDR4), JESD2794/JESD2794A (DDR4), and JESD793E/JESD793F/JESD7931A (DDR3/DDR3L). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk.
Note 2:
Bytemode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification).
Note 3:
The memory vendors often do not offer so many variants of singlechannel memory devices. As an alternative, a dualchannel device with only one channel connected may be used. For example:
A dualrank, singlechannel device with 16row address bits has a density of 16Gb. If such a device is not available at the chosen supplier, a dualrank, dualchannel device with 16row address bits can be used instead. This device has a density of 32 Gb however since only one channel can be connected to the SoC, only half of the density is available (16 Gb).
Usage of more than one discrete memory chips to overcome market constraints is not supported since only pointtopoint connections are assumed for LPDDR4.
Note 4:
Devices with 17row addresses (R0R16) are not supported by the DDR Controller
Note 5:
The memory part number did not undergo full JEDEC verification however, it passed all functional testing items.
Note 6:
The density can be achieved by connecting 2 singlerank discrete devices with one 16Gb die each. Since the SoC supports x8 devices and also has connectivity for a second rank, usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 32Gb/4GB of address space dedicated for the DDR. Two x16 16Gb devices giving 32Gb/4GB in total is, therefore, the optimal choice that balances the maximum density aspects, the signal integrity aspects (only two discrete devices used), and bandwidth aspects (full data bus width used).
Note 7:
The density can be achieved by connecting 4 single rank discrete devices with one 16Gb die each, 2 devices connected to each chip select. Since the SoC supports x8 devices, the usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 64Gb/8GB of address space dedicated for the DDR. Four x16 16Gb devices giving 64Gb/8GB in total is the optimal choice that balances the maximum density aspects, the signal integrity aspects (only four discrete devices used), and the bandwidth aspects (full data bus width used).
Note 8:
The density can be achieved by connecting 4 single rank discrete devices with one 16Gb die each, 2 devices connected to each chip select.
Note 9:
The density can be achieved by connecting 4 single rank discrete devices with one 8Gb die each, 2 devices connected to each chip select, or by connecting 2 dual rank discrete devices with two 8Gb dies each. Since the SoC supports x8 devices, the usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 32Gb/4GB of address space dedicated for the DDR. Four x16 8Gb devices giving 32Gb/4GB in total is, therefore, the optimal choice that balances the maximum density aspects, the signal integrity aspects (four discrete devices used), and bandwidth aspects (full data bus width used).
Note 10:
The density can be achieved by connecting 8 single rank discrete devices with one 8Gb die each, 4 devices connected to each chip select or by connecting 4 dual rank discrete devices with two 8Gb dies each. Note that the first option significantly exceeds the number of devices used on the validation board (4 discrete devices) therefore, it is not guaranteed that the i.MX would be able to drive the signals with margin to the required voltage levels due to increased loading on the traces. A significant effort would be required in terms of PCB layout and signal integrity analysis. Practically, it is not recommended to use more than 4 discrete DDR3L devices. This corresponds to the maximum density of 32Gb/4GB in the case of the single rank devices containing one 8Gb die or 64Gb/8GB in case of the dualrank devices, each containing two 8Gb dies.
Note 11:
The density can be achieved by connecting 4 single rank discrete devices with one 8Gb die each, 2 devices connected to each chip select or by connecting 2 dual rank discrete devices with two 8Gb dies each.
Note 12:
For singlechannel (x16) memory devices, the current maximum available density in the market is 16Gb/2GB (Q1 2022).
Note 13:
Only one channel of the device (and hence, half of its density) was utilized due to the reduced data bus width (x16) of the SoC.