Workaround for de-rating i.MX 8QM/QP parts before SCFW 1.16.0 releases

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For more information about the i.MX 8QM/QP revision, please see the attached PDF slide deck at the bottom of this page. It includes frequently asked questions and is the official source of information regarding this revision.

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The i.MX 8QM and i.MX 8QP has been revised with lower clock speeds and higher core voltages to help improve instability issues found with the part. Old parts that have not been derated have an "FF" moniker in the part number, whereas new parts, releasing in June 2024, have an "FE" moniker. An example can be found below.

SCFW (System Controller Firmware) 1.16.0, which will be released with the Q2 Linux Factory BSP (LF6.6.y_2.0.0), will make the necessary changes to increase core voltage for CPU and GPU cores in the 8QM/8QP, as well as reduce clock speeds.

It may not be immediately apparent what changes must be made to derate these processors before the new parts and new SCFW version is released. To assist with these issues, we are providing the changes below as a workaround until SCFW 1.16.0 is released.

Recommended Changes until SCFW 1.16.0 is released

1. Increase voltages in pmic_init(). This function is found inside the respective board.c file within the SCFW porting kit. This is assuming that the customer has routed their VDD_A72 to PMIC_0 on SW3 and SW4, and routed their VDD_GPU0 and VDD_GPU1 to PMIC_1 on SW1 through SW4.

            +/* Set VDD_A72 to 1.1375V (1138mV) */

            +BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW3, 1138, REG_RUN_MODE))

            +BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW4, 1138, REG_RUN_MODE))



            +/* Set VDD_GPU0 and VDD_GPU1 to 1.03125V (1032mV) */

            +BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_SW1, 1032, REG_RUN_MODE))

            +BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_SW2, 1032, REG_RUN_MODE))

            +BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_SW3, 1032, REG_RUN_MODE))

            +BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_SW4, 1032, REG_RUN_MODE))

2. Add +37.5mV offset for VDD_A72, +31.25mV offset for VDD_GPU0/VDD_GPU1. This is done in the function board_set_voltage, found in board.c of the respective processor in the SCFW porting kit. This ensures that voltages are set correctly if a frequency change occurs (like going from overdrive to nominal mode on GPU).

/*--------------------------------------------------------------------------*/
/* Set the voltage for the given SS. */
/*--------------------------------------------------------------------------*/
sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt)
{
sc_err_t err = SC_ERR_NONE;
pmic_id_t pmic_id[2] = {0U, 0U};
uint32_t pmic_reg[2] = {0U, 0U};
uint8_t num_regs = 0U;

+// A72 cores are running on 1.1375V instead of 1.10V
+if ((ss == SC_SUBSYS_A72) && (new_volt == 1100)) {
+board_print(3, "Changing voltage from 1100 to 1138");
+new_volt = 1138;
+}

+// GPU is running on 1.03125V instead of 1.00V
+if ((ss == SC_SUBSYS_GPU_0 || SC_SUBSYS_GPU_1) && (new_volt == 1000)) {
+board_print(3, "Changing voltage from 1000 to 1032");
+new_volt = 1032;
+}

board_print(3, "board_set_voltage(%s, %u, %u)\n", snames[ss], new_volt,
old_volt);

board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs);

3. Remove 1.6GHz from Linux DTS OPP Table for A72 core. This is found in the device tree of the board. These are typically found in /arch/arm64/boot/dts/freescale/.

/*

        opp-1596000000 {

            opp-hz = /bits/ 64 <1596000000>;

            opp-microvolt = <1100000>;

            clock-latency-ns = <150000>;

            opp-suspend;

        };

*/

4. Disable GPU overdrive mode - set to nominal mode using sysfs in Linux userland

echo "nominal"     >  /sys/bus/platform/drivers/galcore/gpu_govern