RESET pin

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RESET pin

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eishishibusawa
Contributor III

Dear Sir

 

I refer to the VYBRIDFSERIESEC Rev.9.

It is described as the follows at P69 NOTE.

"RESET pin has a external weak pull UP requirement if LPDDR2 memory is required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on."

 

Q1.

Which is the RESET pin either T4 (RESET / RESET OUT) or D6 (DDR_RESET)?

 

Best Regards,

Eishi SHIBUSAWA

 

Dear NXP member

How about this case?

Would you please reply.

 

Best Regards,

Eishi SHIBUSAWA

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We are marking this post as solved, due to the either low activity or any reply marked as correct.

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richard_stulens
NXP Employee
NXP Employee

Hello Eishi ,

It is the DDR_RESET pin that is meant here.

The pull-up is needed to prevent the pin to float when the core supplies are turned off in LPSTOP modes. IF the DDR device needs to retain the content in self-reset mode, then the pin must be pulled high  (RESET negated).

Best regards,

Richard