LPDDR2 Core Clocking with SYS_DIV_OUT_CLK

[jonpartee]

Configuring PLL1 PFD3 as the system synchronous clock at 396 MHz I have configured the CCM_CCSR(DDRC_CLK_SEL] = 1'b1  and we are getting no clock to the DRAM controller core.  I am monitoring the clocks on CKO1 and CK02.  I set the flags to see the ARM A5 core clock and I see the 396 MHz clock but when I switch to the DRAMC clock we get no clocks.

ARM_DIV = 1

BUG_DIV = 3

IPG_DIV  = 2

PLL2 thru PLL 7 are disabled.

and

CCGR6 = 0xFFFFFFFF

Not sure what I am missing to enable this.

*******************************************************************************************************************

*

*

*  Solution has been found it seems to be a bug in the silicon.  Could somebody at Freescale verify this.

*

*

*******************************************************************************************************************

For the DRAMC clock GL MUX to work properly both the PLL2 PFD2 Clock and SYS_DIV_OUT_CLK must

be active when the CCM_CCSR[DDRC_CLK_SEL] bit is set to configure it from its default of

[PLL PFD2 selection] 1'b0.  By having the PLL PFD2 clock running the DRAMC clock output can switch to

the SYS_DIV_OUT_CLK.  Following is the code we used to configure the clock tree in our system and it

works around this issue.

  /*******************************************************

   * Setup the clocks to run in synchronous mode

   * using PLL1 PFD3. The rest of the system  uses PLL1 PFD 4

   * at the same frequency

   */

   /* CCM_CCGR1

      WDOG-M4, WDOG-A5, TCON0, RSVD, ADC0, RSVD, FTM1, FTM0, PIT, PDB, RSVD, USBC0, CRC, SAI3, SAI2, SIA1

           00,      00,    00,   00,   00,   00,   00,   00,  00,  00,   00,    11,  00,   00,   00,   00

   */

  CCM->CCGR1 = 0x00000300;

   /* CCM_CCGR2

      RSVD, RSVD, PORT E MUX, PORT D MUX, PORT C MUX, PORT B MUX, PORT A MUX, IOMUX, RSVD, RSVD, RSVD, QUADSPI0, RSVD, RLE, RSVD, LPTMR

        00,   00,         11,         11,          11,         11,        11,    11,   00,   00,   00,       00,   00,  00,   00,    00

   */

   CCM->CCGR2 = 0x0FFF0000;

   /* CCM_CCGR3

      RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, DCU0, RSVD, RSVD, RSVD, RSVD, RSVD, SCSCM, RSVD, ANADIG

        00,   00,   00,   00,   00,   00,   00,   00,   00,   00,   00,   00,   00,    01,   00,     01

   */

   CCM->CCGR3 = 0x00000011;

   /* CCM_CCGR4

      ASRC, SPDIF, ESAI, RSVD, RSVD, EWM, I2C 0, I2C 1, RSVD, RSVD, WKUP, CCM, GPC, VREG_DIG, RSVD, CMU

        00,    01,   00,   01,   01,  01,    00,    00,   00,   00,   00,  00,  00,       00,   00,  00

   */

   CCM->CCGR4 = 0x11500000;

   /* CCM_CCGR5 --> reserved */

   /* CCM_CCGR6

      RSVD, DDRMC, SPI3, SPI2, RSVD, UART5, UART4, WDOG_SNVS, SNVS, RSVD, OTP_CTRL, RSVD, RSVD, DMA3, DMA2, RSVD

        00,    11,   00,   00,   00,    00,    00,        00,   00,   00,       00,   00,   00,   00,   00,   00

   */

   CCM->CCGR6 = 0x30000000;

   /* CCM_CCGR7

      RSVD, LCD, TCON1, RSVD, ADC1, RSVD, FTM3, FTM2, RSVD, RSVD, RSVD, USBC1, RSVD, SDHC1, SDHC0, RSVD  -->

        00,  00,   00,    00,   00,   00,   00,   00,   00,   00,   00,    11,   00,    11,    11,   00 -->

   */

   CCM->CCGR7 = 0x0000033C;

   /*  CCM_CCGR8 thru CCM_CRGR11

       No modules used in these register

   */

  CCM->CCGR8 = 0x0;    //Turn off GPU since causes immediate interrupt

  CCM->CCGR9 = 0x0;

  CCM->CCGR10 = 0x0;

  CCM->CCGR11 = 0x0;

   /* enable the external oscillator */

   /*  CCM_CLPCR

         Clear FXOSC_PWRDWN bit before enabling external fast oscillator.

   */

   CCM->CLPCR = 0x00000078;

   /*  CCM_CCR

       Enable external fast oscillator.

   */

   CCM->CCR = 0x00011000;

   /*  ANADIG_ANA_MISC0

       Clear ANA_MISC0[CLK_24M_IRC_XTAL_SEL] to select among external and internal fast oscillator.

   */

   ANADIG->ANA_MISC0 = 0x00000000;

   /*  Enable and configure PLLs  */

   /* PLL 1

     [18] PFD_OFFSET_EN = 1'b0

     [17]DITHER_ENABLE  = 1'b0

     [16]BYPASS         = 1'b0

     [14]BYPASS_CLK_SRC = 1'b0

     [13]ENABLE         = 1'b1

     [12]POWER_DOWN     = 1'b0

     [0] DIV_SELECT     = 1'b1

   */

   ANADIG->PLL1_CTRL = 0x00002001;

   ANADIG->PLL1_PFD  = 0x18181593;

   /* PLL 2 PFD2 is only configured due to an issue with the DRAMC clock mux. 

      These are disabled after the clocks are set up

   */

   ANADIG->PLL2_CTRL = 0x00002001;

   ANADIG->PLL2_PFD  = 0x98981898;

   /* Configure MUX selectors for core, bus and peripheral clocks.

      CCM_CCSR:

                [31] PLL3_PFD4_EN = 1'b0

                [30] PLL3_PFD3_EN = 1'b0

                [29] PLL3_PFD2_EN = 1'b0

                [28] PLL3_PFD1_EN = 1'b0

                [24] DAP_EN= 1'b0

                [21:19] PLL2_PFD_CLK_SEL = 3'b000 -> PLL2 main clock

                [18-16] PLL1_PFD_CLK_SEL = 3'b011 -> PLL1 PFD3 clock

                [15] PLL2_PFD4_EN = 1'b0

                [14] PLL2_PFD3_EN = 1'b0

                [13] PLL2_PFD2_EN = 1'b0

                [12] PLL2_PFD1_EN = 1'b0

                [11] PLL1_PFD4_EN = 1'b1

                [10] PLL1_PFD3_EN = 1'b1

                [ 9] PLL1_PFD2_EN = 1'b1

                [ 8] PLL1_PFD1_EN = 1'b0

                [ 6] DDRC_CLK_SEL = 1'b1 -> SYS_DIV_OUT_CLK

                [ 5] FAST_CLK_SEL = 1'b1 -> FX0SC clock

                [ 4] SLOW_CLK_SEL = 1'b0 -> IRC clock

                [2:0] SYS_CLK_SEL = 3'b100 -> PLL1_PFD_CLK_SEL

   */

   /* Issue cannot use 0x00030E64 directly because the DDRC_CLK_SEL mux will

      not switch to right clock source without PLL2 PFD2 Clock

   */

   CCM->CCSR = 0x00032E64;

   /* Configure clock dividers for core, bus and peripheral clocks.

      CCM_CACRR:

                [24:22] FLEX_CLK_DIV = 3'b000

                [21] PLL6_CLK_DIV = 1'b0

                [20] PLL3_CLK_DIV = 1'b0

                [17:16] PLL1_PFD_CLK_DIV = 2'b00

                [12:11] IPG_CLK_DIV = 2'b01

                [8:6] PLL4_CLK_DIV = 3'b000

                [5:3] BUS_CLK_DIV = 3'b010

                [2:0] ARM_CLK_DIV = 3'b000

                  28   24   20   16   12    8    4    0

                0000_0000_0000_0000_0000_1000_0001_0000

   */

   CCM->CACRR = 0x00000810;

   /* PLL 3 -> Disabled at start up is enabled by software

               when the USB port is connected.  USB is the only

               device that uses this PLL.

   */

   ANADIG->PLL3_CTRL = 0x00001001;

   /* PLL 4 -> disabled  */

   ANADIG->PLL4_CTRL = 0x00001001;

   /* PLL 5 -> disabled  */

   ANADIG->PLL5_CTRL = 0x00001001;

   /* PLL 6 -> disabled  */

   ANADIG->PLL6_CTRL = 0x00001001;

   /* PLL 7 -> disabled  */

   ANADIG->PLL7_CTRL = 0x00001001;

  /* Disable PLL2 now that the DRAMC clock mux has been configured

  */

    ANADIG->PLL2_CTRL = 0x00001001;

    CCM->CCSR = 0x00030E64;

[naoumgitnik]

Dear Jon,

Before we dig deeper, have you checked our software provided on the web to see how the relevant registers are handled there?

Sincerely, Naoum Gitnik.

[jonpartee]

Naoum,

The SystemInit function in the system_Vybrid.c file uses PLL2 in all its clocking schemes.  So this would not have been found.

Jp

[ioseph_martinez]

Jon,

I will take a look into this the following days.

Just want to clarify a doubt I have:

For the DRAMC clock GL MUX to work properly both the PLL2 PFD2 Clock and SYS_DIV_OUT_CLK must

be active when the CCM_CCSR[DDRC_CLK_SEL] bit is set to configure it from its default of

[PLL PFD2 selection] 1'b0.  By having the PLL PFD2 clock running the DRAMC clock output can switch to

the SYS_DIV_OUT_CLK.  Following is the code we used to configure the clock tree in our system and it

works around this issue.

In few words:

if PLL2_PFD2 clk is not running you can't switch clocks with DDRC_CLK_SEL to SYS_DIV_OUT_CLK

if PLL2_PFD2 clk is running you can switch clocks with DDRC_CLK_SEL to SYS_DIV_OUT_CLK

Is that correct?

[jonpartee]

Loseph,

     You are correct, if PLL2_PFD2 clk is not running you can't switch clocks with DDRC_CLK_SEL to SYS_DIV_OUT_CLK.

Jp

[ioseph_martinez · Accepted solution]

Jon, I confirmed internally this. It is not really a bug but a documentation fault, since we are not mentioning it. Based on the feedback GL MUX requires both clocks to be active when switching clocks. I will raise an internal note to have it documented on the next release.

Thanks for finding this and providing feedback.

[ioseph_martinez]

Jon,

I am seeing similar behavior. Both PLL2 and PLL2_PFD2 must be enabled if switching DDR clocks.

Will check internally and get back to you with a conclusion.

/ioseph.