I2C Clock Stretching in Vybrid

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

I2C Clock Stretching in Vybrid

Jump to solution
1,693 Views
srebbago
Contributor I

Hi ,

I want to know how to enable I2C clock stretching in Vybrid F-series. In reference manual(VYBRIDRM.pdf), I have found the below data(snap shot). But, didn't get information about which register/pin will set clock stretching. or Is clock stretching is enabled default in Vybrid?.

Give me clarification on this ASAP.

Thank you.pastedImage_0.png

Labels (3)
0 Kudos
1 Solution
1,373 Views
CommunityBot
Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

View solution in original post

0 Kudos
2 Replies
1,374 Views
CommunityBot
Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!
0 Kudos
1,374 Views
jiri-b36968
NXP Employee
NXP Employee

Hello Siva,

clock stretching is a feature of I2C itself. It is always enabled. Any slave can slow down data transfer controlled by the master by holding CLK low for necessary time after the master sets CLK low. The master will continue with transfer once CLK is released.

/Jiri