Binary Loading : TCM and OCRAM

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Binary Loading : TCM and OCRAM

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carlovalgocela
Contributor III

Hello

In Vybrid Architecture manual, a TCM backdoor is intended to load the code and data into TCM by Cortex-A5 (primary core) prior to running Cortex-M4 (secondary core).

It actual it is loaded in the OCRAM-SysRAM0.  Can anybody explain why it is loaded in SysRAM0 and not in the TCM?

Thanks

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This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

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jiri-b36968
NXP Employee
NXP Employee

Hello Carlo,

missing some information like which code or data, what project...

Anyway, generally the placement of the code and data depends on Linker command file (IAR) - see supp.iar.com or scatter file  (DS5) - see Loading this site

Depending on your IDE you can select location of your code and date and build the project with this setting. Then your code will be placed where you want.

/Jiri