Determining T1042 timebase frequency

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Determining T1042 timebase frequency

295 Views
nakrachi
Contributor II

Hi Everyone,

We are trying to determine the right frequency at which the timebase is updated. 

According to the reference manual the core timebase frequency is calculated as follows :

Timebase clock = (platform_clock/16) / TBCLKDIVR

in our case :

  • Platform clock is 600 Mhz
  • RCPM_PCTBCKSELR is 0 -> Core Timebase is clocked with Platform Clock /16
  • TBCLKDIVR is 0x2 -> 1/8 

so our timebase frequency should be : 600/(16*8) = 4.6875 Mhz 

but when measuring with the logic analyzer we get a timebase frequency of 50Mhz.

I would like to confirm if I a calculated the right frequency or if I missed something, 

thank you 

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18 Replies

263 Views
nakrachi
Contributor II

The only pin available to me was the UART_SOUT which I had to configure as GPIO1[15] by modifying the RCW. 

I used the debugger RCW override function to use my new RCW, I figured out that the debugger will set the platform PLL to 4:1 even though my RCW is setting it to be 6:1. meaning that my platform clock is 400 Mhz and not 600 Mhz (SYSCLK is 100Mhz). 

which make a little bit more sense, if we consider that platform clock is only divided by TBCLKDIVR, 400Mhz/8 = 50 Mhz

 I think that "RCPM_PCTBCKSELR is 0 -> Core Timebase is clocked with Platform Clock /16" statement is not true. 

Can you please confirm.

thank you

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291 Views
ufedor
NXP TechSupport
NXP TechSupport

You wrote:

> when measuring with the logic analyzer we get a timebase frequency of 50Mhz

How exactly you did that?

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287 Views
nakrachi
Contributor II

Thanks for the reply,

I did set the decrementer to a value of 50000 ticks 

nakrachi_2-1632384793385.png

with Auto reload enabled (TCR= 0x0000000000400000) 

then in the decrementer exception vector (IVOR10) I toggle a GPIO which I measure with the logic analyzer. 

I get a frequency of 1Khz (a period of 1 ms) 

nakrachi_1-1632384535876.png

which makes me believe I am running at 50 Mhz (50000 * 1Khz) 

 

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265 Views
ufedor
NXP TechSupport
NXP TechSupport

DECAR in your case is zero.

 

 

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260 Views
nakrachi
Contributor II

The debugger can't read it (according to core manual "The DECAR contents cannot be read") 

but I know that I wrote the right value and I am getting decremented exceptions at a fixed interval. 

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233 Views
ufedor
NXP TechSupport
NXP TechSupport

Please show using Trace32 values of:

RCPM_PCTBCKSELR

RCPM_TBCLKDIVR

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nakrachi
Contributor II

Here is a screenshot

nakrachi_0-1632473780471.png

 

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221 Views
ufedor
NXP TechSupport
NXP TechSupport

What is SYSCLK frequency?

Please provide U-Boot booting log.

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219 Views
nakrachi
Contributor II

The system frequency is 100MHz 

here is the u-boot log 

nakrachi_0-1632474272424.png

 

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217 Views
ufedor
NXP TechSupport
NXP TechSupport

600/50=12

I have no idea how such ratio can be obtained.

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ufedor
NXP TechSupport
NXP TechSupport

Please combine all consistent experimental data into single Word or PDF document.

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209 Views
nakrachi
Contributor II

just making sure, you want me to describe the issue with relevant data/screenshots and post it here ?

thanks

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ufedor
NXP TechSupport
NXP TechSupport

Yes, please.

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nakrachi
Contributor II

@ufedor please fin attached the requested document. 

Thanks

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nakrachi
Contributor II

Hi @ufedor , just following up on this.

thanks

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ufedor
NXP TechSupport
NXP TechSupport

Your understanding is correct.

Time base frequency = (Platform clock )/RCPM_TBCLKDIVR When RCPM_PCTBCKSELR [PCTBCKSELn] = 0, Core Timebase is clocked with Platform Clock/ RCPM_TBCLKDIVR [tbclkdiv].

It is recommended to have the default value of RCPM_TBCLKDIVR [tbclkdiv], i.e., 0x00 : 1/16. This field should not be modified by customer as all the testing are done with Timebase clock divider configuration = 1/16.

Comment is added in T1042RM.

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nakrachi
Contributor II

Thank you,

But then we have another problem, the erratum A-010651 states that the workaround is changing the RCPM_TBCLKDIVR [tbclkdiv], to 0x08 : 1/32.

but you mentioned we should not change it. how can we workaround this errata then ?

thanks

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215 Views
nakrachi
Contributor II

Thanks for the quick replies,

as I mentioned in an earlier comment, I found out that using the temporary RCW has set my PLL ration to 4:1 so I was running at 400Mhz when I got 50Mhz. 

Now after setting back the platform clock to 600Mhz  I measure a time base frequency of 75Mhz. (600/8)

which makes me believe that the user manual is wrong

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