MC33771C - Design questions (Possibly obvious)

[Poley]

Hi all, I have some questions for a MC33771C board design that might be stupid questions.

1. VPWR - Does this just connect to the positive sid of the cell you have for cell 14? If so, why do all of the development boards have a seperate VBAT input on the connectors? Do I need to power the IC from an external source or is this definitely powered by the 12 cell stack that the IC is monitoring?

2. GND - Similar to question 1, do I just use the negative side of cell 1 (Cell 0)? How is this different to CT_REF?

3. If question 2's answer is that you just use cell 0 for ground - For on-board capacitive isolation, would the joining of ground now cause any issues with cells shorting for the next MC33771C? Forexample I have 3 IC's on 1 board to monitor 36 cells. Would following the reference design with the HVBMS not short my first 12 cells?

Again, apologies if any of this is me missing the obvious, I have gone through the datasheet and all of the secure files and I can not find a definite answer on how this schematic should look,

Thank you!

[guoweisun]

Thanks for your questions, please follow below link download schematic for getting more detail information:

FRDM33771CSPEVB | SPI Evaluation Board for MC33771C | NXP Semiconductors

[Poley]

Hi @guoweisun 

I have been though all of the schematics but unfortunately none of them clearly answer any of the questions I have asked. They all still have separate inputs on their connector for power and ground and also no info on ground sharing through capacitive isolation shown in my question.

thanks