S32G Bist effecting latenet failure rate?

[Daniel_Wax]

Waymo plans to run BIST during the bootup phase of S32G, not the runtime. They are wondering how much diagnostic coverage this can help to achieve. Also, we have concerns that the BIST might affect Latent failure rate. Will BIST at Reset cause a failure rate increase-in-time? Do we need to keep a frequency of BIST test to maintain the failure rates to be acceptable?

I dont see anything in the FMEDA about this

[nxa11829]

Hi,

The BIST can be run at either startup or shutdown, it will always be followed by a functional reset of the chip. The point in time when BIST is run does not affect the diagnostic coverage.

There are two main configurations of BIST: Safety DCD and Safety Boot, both can be run at startup or shutdown as desired. 85% diagnostic coverage is achieved by LBIST and 99% diagnostic coverage by MBIST on the logic / memories tested.

The BIST should be run at least once per multiple-point fault detection time interval if it is to be used as a measure to detect latent faults.

See the file S32G_Bist_Configurations.xlsx available as part of the S32G SAF BIST software download for details of the BIST configurations.