manage ADC on dual core(S32K324)

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manage ADC on dual core(S32K324)

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michelet1
Contributor II

Good morning everyone,

i was analyzing code of the following ref design:

https://www.nxp.com/document/guide/getting-started-with-the-mctptx1ak324-evaluation-board:GS-MCTPTX1...

and in this case ADC channels were all associated with core0.

My question is the following: is it possible to separate ADC instances so as to have for example ADC0 on core0 and ADC1,ADC2 on core1? or is there some limitations?

Thanks in advance for any help and guidance.

Best regards

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_Leo_
NXP TechSupport
NXP TechSupport

Hi,

Thank you so much for your interest in our products and for using our community.

In MCTPTX1AK324 demo code, ADCs 0/1/2 were managed by core 0 and core 1 could get conversion results by sharable memory. This configuration were for application purposes.

However with the XRDC you can manage access control between masters (cores and noncore masters) and targets (memories and peripherals) by placing them in domains. You can read more about it in Chapter 19 Extended Resource Domain Control from reference manual.

Hope it helps you.

Have a nice day!

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232件の閲覧回数
_Leo_
NXP TechSupport
NXP TechSupport

Hi,

Thank you so much for your interest in our products and for using our community.

In MCTPTX1AK324 demo code, ADCs 0/1/2 were managed by core 0 and core 1 could get conversion results by sharable memory. This configuration were for application purposes.

However with the XRDC you can manage access control between masters (cores and noncore masters) and targets (memories and peripherals) by placing them in domains. You can read more about it in Chapter 19 Extended Resource Domain Control from reference manual.

Hope it helps you.

Have a nice day!

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michelet1
Contributor II

Good morning,

thanks for your suggestions.

I looked at chapter 19 of the reference manual but a doubt arose: i can dedicate peripheral instances to specific cores( e.g. ADC0 for core0 and ADC1,ADC2 for core1) and then exploit XRDC to create domains so that, for example , core1 cannot access ADC0 because it is already allocated on core0, is this reasoning correct?

thanks again for the help

best regards

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_Leo_
NXP TechSupport
NXP TechSupport

Your understanding is correct!

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