I have a question. For my project, I need to acquire the voltage values of CAN-High and CAN-Low and at the same time I want to store the Identifier of CAN-message that is received.
The clock of ADC is FIRCDIV2_CLK, while the clock source of CAN is SOSCDIV2.
For the reason that I need to have a synchronization between the start of transmission of CAN message and start of sampling of ADC, I wrote a code where if the value of ADC0, that acquires CAN-Low, is lower than a threshold_low and if the value of ADC1, that acquires CAN-High, is higher than threshold_high, so I stored in two Buffers (CAN-High, CAN-Low) the voltage values of two signals. This is due to the fact that, the first bit transmitted is the start of frame, that in binary term is equal to 0. From theorical point of view, when there is a 0 on the bus, the bit is dominant. One bit dominant, in terms of voltage, is equal to 3.5V on CAN-High and 1.5V on CAN-Low.
If I want to add the function FlexCAN_receive in order to obtain for each buffers of voltage measurements, the ID of that CAN message, how could I do this? I need to obtain the relationship between ID received and the voltage measurements of two cable.
I attach my code so that if someone could help me, I'm very grate.
as per your code you do in while loop following
1. SW start ADC conversion on both ADCs
2. waits for conversion complete
3. once first "dominant sample" is detected ADC results are starting to be saved into a buffers and steps 1-3 are repeated until buffers are full
4. then buffers content is compared with the ID of received frame
What is the result you got?
If you have ADC conversion time about 1us+some SW overhead and CAN bitrate at 50kbps (bit time 20us) you have quite big oversample ratio. It can be OK, but you have to properly interpret the result.
Also instead of SW start of ADC it should be better to use HW trigger, eg. using PBD and trigger ADC at given rate according to CAN bit time.
Another note; even if you will sample bus signals properly you will need to remove possible stuff bits which exists on CAN bus and which are added/removed by FlexCAN module.
thanks for your help. I use a software trigger for ADC0 and ADC1. They have as clock FIRCDIV2_CLK so that fADC is equal to 48MHz. The CAN bus is configured to receive the CAN message with bit rate equal to 50Ksamples/second. I have a good results because I'm able to store the voltage values and at the end of transmission of message, I read the ID of that message. But I have some doubts about the clock. I don't understand how to comprehend the sampling of ADC. In fact, it's ok that I read the voltage values, but how this voltage measurements are correct?
So that, for the Manual I know that there is a time conversion formula of ADC. In addition I use the library <elapsed_time.h> for measuring the clock cycle before and after the conversion of ADC. The difference of clock cycle is equal to 963. But this quantity I should divided by the core clock. For the fact that the ADC has as clock FIRCDIV2 and the CAN bus SOSCDIV2, what is the core clock of the board?
Finally, in your opinion if I use a hardware trigger I don't have this problem?
Thanks for your help
as per feedback in your other post...If you use DWT to measure the execution time and the count difference is 963, then the elapsed time is 963 / CORE_CLK (SYS_CLK).
In your code you call NormalRUNmode_80MHz, thus CORE_CLK should be 80MHz.
Elapsed time is then 963/80MHz = 12.04us.
Using hardware trigger you can precisely control a time when ADC conversion is started with respect of trigger signal (e.g. external signal edge).