[Security] Encrypt and decrypt concurrent design issues using CSEC

[Gideon]

Dear NXPs:

S32K146 with FreeRTOS.

When the three peripherals I2C.SPI.UART send and receive data, they will use CSEC's AES128 CBC algorithm for encryption and decryption. There are concurrency scenarios in the data sending and receiving of these three peripherals.
Q1: Can the CSEC hardware encryption and decryption module handle concurrent encryption and decryption scenarios?
Q2: If Q1 is not met, how to solve the encryption and decryption requirements in concurrent scenarios?

[lukaszadrapa · Accepted solution]

Hi @Gideon 

no, CSEc can execute one command only at a time. You need to wait until shared resources are released - i.e. you can use semaphores.

Regards,

Lukas